- Cadence Design Systems (San Jose, CA)
- Lead Applications Engineer DDR Design IP page is loaded## Lead Applications Engineer DDR Design IPlocations: SAN JOSEtime type: Full ... matter where you are in your career. As a Lead Technical Presales Engineer , you will use...standards to architect memory solutions for customers using Cadence DDR IP. This role offers the benefit of both… more
- Lattice (San Jose, CA)
- …FPGA consists of various IPs as a building block such as SERDES(PMA/PCS), Memory DDR (DDR4, LPDDR4, DDR5 etc), DPHY, PLL, DSP, Fabric, I/O etc. As a Silicon Design ... Validation engineer , you will have an opportunity to learn and...learn FPGA and it's build block such asSERDES(PMA/PCS), Memory DDR (DDR4, LPDDR4, DDR5 etc), DPHY, PLL, DSP, MIPI, Fabric,… more
- Cadence Design Systems (San Jose, CA)
- Sr Principal Product Engineer - Memory IP page is loaded## Sr Principal Product Engineer - Memory IPlocations: SAN JOSEtime type: Full timeposted on: Posted ... electronic products-from chips to boards to systems-for dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace,… more
- Amazon (San Francisco, CA)
- …engineers to join the Pre‑silicon Verification team and help us technically lead the challenges of the next decade, developing a semiconductor platform based ... develop into a better‑rounded professional. Basic Qualifications Electrical/Computer Science engineer . Please include a grade sheet/academic transcript along with… more
- Amazon (San Francisco, CA)
- …engineers to join the Pre‑silicon Verification team and help us technically lead the challenges of the next decade, developing a semiconductor platform based ... you develop into a better‑rounded professional. Basic Qualifications Electrical/Computer Science engineer 5+ years of experience with RTL verification Knowledge of… more
- Arm Limited (San Jose, CA)
- …of the future! Job Overview: We are looking for a Principal UEFI Firmware Design Engineer to lead and drive the development of UEFI firmware across server and ... roadmap, and execution of next-generation platform management firmware. Responsibilities: Lead the architecture, design, development, and deployment of UEFI-based… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …a difference and be challenged? Join the High-Performance Culture at Cadence. As a Lead Technical Presales Engineer , you will use your knowledge of different ... smart, energetic, collaborative and creative people to help us lead the industry with our IP products. At Cadence,...standards to architect memory solutions for customers using Cadence DDR IP . This role offers the benefit of… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …and innovators who want to make an impact on the world of technology. Senior Applications Engineer - DDR Design IPJob Location: San Jose, CAJob ... smart, energetic, collaborative and creative people to help us lead the industry with our IP products. At Cadence,...Engineer , you will support the technical presales of DDR IP by generating collateral through simulations, synthesis and… more
- Meta (Menlo Park, CA)
- **Summary:** Meta is seeking a versatile Hardware Engineer to join our Compute Hardware team. Our mission is backed by a massive hardware infrastructure. Our ... cutting-edge data centers affecting billions of users. **Required Skills:** Hardware Engineer Responsibilities: 1. Work with local and remote teams and suppliers,… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …products-from chips to boards to systems-for dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace, ... Join our growing and dynamic IP team and help lead the proliferation of best-in-class Memory PHY IP products...of high-performance IP related to memory protocols such as DDR , LPDDR, HBM, and GDDR, and to engage with… more
- Insight Global (Fremont, CA)
- Job Description The BIOS/UEFI Firmware Engineer is responsible for the architecture, design, development, and debugging of UEFI (Unified Extensible Firmware ... (SEC), Pre-EFI Initialization (PEI), and Driver Execution Environment (DXE). * Lead effort in hardware bring-up for new platforms, debugging complex… more
