- Cadence Design Systems (San Jose, CA)
- …SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing, Distributed and Concurrent STA flows. Collaborate with R&D and customers to enable timing analysis ... & ECO flows, including advanced technologies. Perform timing correlation, tool feature benchmarking, constraints validation, spice analysis on various tech nodes and customer designs. Work on in-design timing ECO optimizations with knowledge of Place and… more
- Cadence Design Systems (San Jose, CA)
- Sr Principal Product Engineer - Memory IP page is loaded## Sr Principal Product Engineer - Memory IPlocations: SAN JOSEtime type: Full timeposted on: ... making an impact in our world.We are seeking a Post Silicon Memory Product Engineer to support silicon bring-up, debug, and production ramp for advanced memory IP… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …an impact in our world. We are seeking a Post Silicon Memory Product Engineer to support silicon bring-up, debug, and production ramp for advanced memory IP ... and recommendations to customers. + Analyze and resolve complex subsystem application or implementation issues. + Contribute to documentation, checklists, and… more
