- Altera (San Jose, CA)
- Altera . Timing Engineer / Lead page is loaded## Timing Engineer /Leadlocations: San Jose, California, United Statestime type: Full timeposted on: Posted ... to becoming the world's #1 FPGA company!**About the Role**Altera is looking for a Timing Engineer to lead timing activities for a subsystem. This person… more
- Altera (San Jose, CA)
- A leading technology company in San Jose, California, is seeking a Timing Engineer to lead timing activities for subsystems. This role requires extensive ... experience in timing analysis and sign-off, as well as proficiency with...proficiency with scripting languages. The ideal candidate will drive timing closure and collaborate closely with design teams. A… more
- Altera (San Jose, CA)
- …per Watt leadership for every product in our broad portfolio.As a **Silicon Design Engineer (Power Technical Lead )**, you will have the opportunity to drive full ... product development cycle* Low power circuit design, including some analog* Timing sign-off analysis* Power optimization techniques such as profiling, clock-gating,… more
- Analog Devices, Inc. (San Jose, CA)
- …variety of applications and markets.**The Position:**The group is seeking an experienced Principal Engineer to lead and contribute to the development of next ... Principal Engineer , eFPGA Place and Route page is loaded##...the development and support of FPGA backend toolset including timing -driven implementation suite (optimization, place and route, bitstream), reporting… more
- Altera (San Jose, CA)
- …to becoming the world's #1 FPGA company!**About the Role**As a Sr. Physical Design Tech Lead / Engineer at Altera, you will play a critical role in our backend ... blocks, routing fabrics, I/O rings, on-chip power domains).**Key Responsibilities** Lead and execute physical design implementation tasks (floorplanning, power… more
- Cadence Design Systems (San Jose, CA)
- …knowledge of Place and Route, Clock Tree, RC Extraction, and UPF/CPF concepts. Lead Tempus timing signoff campaigns with existing and new customers. Automate ... customer sites. Requirements: 10+ years of experience in Static timing analysis. Ability to lead and execute...experience in Static timing analysis. Ability to lead and execute technical campaigns with internal and external… more
- Credo Semiconductor, Inc. (San Jose, CA)
- …- because at Credo, We Connect. About the Role As a Senior Physical Design Engineer , you will manage all aspects of physical design and implementation for Credo SoC ... teams in China and Taiwan to ensure successful tapeouts. Responsibilities Lead and drive top-level, IP, and block-level physical implementation from RTL… more
- Cadence Design Systems (San Jose, CA)
- Application Engineer Architect page is loaded## Application Engineer Architectlocations: SAN JOSEtime type: Full timeposted on: Posted 2 Days Agojob requisition ... and level up your communication, customer, and sales skills. Key Responsibilities* Lead a team of Application Engineers providing technical support to Cadence… more
- Encore Semi Llc (San Jose, CA)
- Sr Physical Design Engineer (Remote) Full-time: Salary + Benefits + Bonuses / Contractor Work Status: US citizen or Lawful Permanent Resident. Remote (Anywhere in ... US) Responsibilities Lead full-chip and block-level physical design for advanced semiconductor...clock architectures, placement and routing, and chip assembly. Own timing closure, signal integrity, power, noise, yield, and physical… more
- Renesas Electronics Corporation (San Jose, CA)
- …RTL design, simulation, and release Independently handle complicated design tasks or lead /drive multiple development efforts Chip level synthesis, timing check, ... digital design and verification Hands‑on knowledge and good experience with Synthesis, Timing Check, and DFT design Must have experience in developing digital design… more
- Amazon (San Francisco, CA)
- …fellow designers, verification specialists, pre‑ and post‑silicon validation teams, and synthesis, timing , and back‑end experts. Lead design projects to meet ... Sr. ASIC Design Engineer , Cloud-Scale Machine Learning Acceleration team Amazon Web...area requirements. Implement SystemVerilog RTL, and deliver synthesis and timing ‑clean designs with appropriate constraints. Execute lint and CDC… more
- Chef Robotics (TM) , Inc. (San Francisco, CA)
- …Software Engineer , Planning and Control at Chef Robotics, you'll lead the development of sophisticated motion planning and control systems that orchestrate ... can work start‑up‑oriented hours. Advanced Motion Planning & Trajectory Optimization Lead the development of classical and learning‑based motion planning algorithms… more
- Eridu Corporation (San Francisco, CA)
- …reality contact lens). Position Overview We are hiring multiple positions from Sr. Engineer to Principal Engineer . We are looking for a highly experienced ... deep expertise in networking ASICs and chiplet-based architectures. You will lead bring-up, validation, and characterization of complex multi-die systems integrating… more
- eBay Inc. (San Jose, CA)
- …control, routing, and traffic policy enforcement. We are seeking an experienced engineer (10+ years) with deep expertise in the Linux kernel networking stack ... and production observability to lead design and implementation of high-performance data planes and...and NIC telemetry. Experience with time synchronization and precision timing (PTP), clocking, and its impact on networking performance.… more
- Kubelt (Alameda, CA)
- …a novel optical interconnect for interfacing with the brain and seeking an experienced lead digital IC designer to take a leading role in developing digital IPs and ... the digital design in terms of area, power, and timing is required. Familiarity with high-speed digital interfaces using...testing is required Evidence of exceptional ability as a lead digital IC designer BS in Electrical Engineering Preferred… more
- Cadence Design Systems (San Jose, CA)
- Sr Principal Design Engineer page is loaded## Sr Principal Design Engineerlocations: SAN JOSEtime type: Full timeposted on: Posted Todayjob requisition id: R52250## ... high-performance memory IP architecture design, owning the IC micro-architecture, timing budget, power analysis platform development.* Proficiency in logic design,… more
- Altera (San Jose, CA)
- Altera .Principal FPGA Compiler Software Engineer page is loaded## Principal FPGA Compiler Software Engineerlocations: San Jose, California, United Statestime type: ... optimization algorithms for our FPGA CAD software tools, including timing -driven analytic placement, detailed placement, partitioning and floorplanning* Developing… more
- Analog Group (San Jose, CA)
- The Sr. Digital Design Engineer candidate must have demonstrated success in digital design & verification/infrastructure development for digital FPGAs/ASICs. Other ... design knowledge, backend flow and tools knowledge. Candidate will be expected to lead designer, verification, and be technical focus on one or more device and/or… more
- Recruiting From Scratch (San Francisco, CA)
- …success for both clients and candidates. Title of Role Staff Software Engineer (Voice Agent) Location San Francisco, CA (On-site, 5 days/week) Company Stage ... voice-specific conversational logic across omnichannel environments. What You Will Do Lead the architecture and long-term evolution of the real-time voice runtime.… more
- General Motors (Mountain View, CA)
- …production ECU design changes. We are seeking a high-performing Mechanical Design Engineer interested in leading the in-house development of GM electronics design. ... external customers. Responsibilities: Execute mechanical design of ECUs per program timing , leading to successful launch of the product. Design mechanical components… more
