• HBM/DDR/SerDes DFT Verification Lead

    Broadcom (San Jose, CA)
    …Broadcom's ASIC Product Division is seeking candidates for HBM/DDR/SERDES Verification Lead Engineer position at our San Jose, California Development ... We are seeking a highly skilled HBM and SerDes DFT Verification Engineer to join our dynamic...of our HBM, DDR and SerDes designs through comprehensive Design for Test ( DFT ) verification strategies. You… more
    Broadcom (12/06/25)
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  • DFT Engineer

    Broadcom (San Jose, CA)
    …you apply.** **Job Description:** Broadcom's CSG division is seeking candidate for a DFT lead position. The successful candidate will be responsible for leading ... most complex and cutting edge network switching ASIC DFx ( Design for Test/debug & manufacturability) from DFT ...verbal and written communication skills. + Must be self-driven engineer with good project management and organizational skills to… more
    Broadcom (11/19/25)
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  • Senior Design for Manufacturing, Testing,…

    General Motors (Sunnyvale, CA)
    …the role, it can be either _Warren, MI or Sunnyvale, CA as directe_ d. ** Design for Manufacturing, Testing, Tooling Engineer ** **The Role:** General Motors is at ... internal and external customers. **Responsibilities of the Design for Manufacturing, Design for Testing, Tooling Engineer include:** + Work with cross… more
    General Motors (11/25/25)
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  • Senior Hardware Design Engineer

    General Motors (Mountain View, CA)
    … and development of our vehicle displays hardware. In this role, the Senior Hardware Design Engineer - Display Development will be responsible for the technical ... supplies, SoCs, MCUs, SerDes interfaces, network devices, etc. + Lead design for manufacturing (DFM), design...manufacturing (DFM), design for assembly (DFA), and design for testing ( DFT ) + Drive the… more
    General Motors (12/05/25)
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  • Lead Application Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …who want to make an impact on the world of technology. Job Title: Lead Application Engineer Location: Tampere, Finland Reports to: AE Director Job Overview: ... Cadence EDA tools for Synthesis, Logical Equivalency Checking (LEC), Design -for-Test ( DFT ), Place & Route and Static...questions, and discussions for a given customer engagement + Lead technical discussions with customers and be the primary… more
    Cadence Design Systems, Inc. (12/03/25)
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  • Optomechanical Design Engineer

    Applied Materials (Santa Clara, CA)
    …packaging materials. Support the Product Life Cycle (PLC) process by defining Design For Transportability ( DFT ) requirements and influencing product design ... capable international team to develop advanced photonics packaging solution. You will lead optomechanical design , optical sub-assembly design , micro optics,… more
    Applied Materials (01/08/26)
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  • Circuit Design Engineer - New…

    NVIDIA (Santa Clara, CA)
    …a more exciting time to join our team! We are now looking for a Circuit Design Engineer ! Are you interested in defining the next generation of Hardware for ... and security. Come join us in our mission to engineer the next generation of world class products. What...to stand out from the crowd: + Understanding of Design -for-test ( DFT ) and logic design .… more
    NVIDIA (01/10/26)
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  • Senior Circuit Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a motivated Senior Circuit Design Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role in ... the entire line of products. + Be a mentor/technical lead for junior team members. What we need to...verification, knowledge of Place and Route, and understanding of Design -for-test ( DFT ) is a plus. + Proficiency… more
    NVIDIA (01/03/26)
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  • Sr. RTL Design Engineer - Wireless…

    Amazon (Sunnyvale, CA)
    …in locations without reliable connectivity. Come work at Amazon! We're hiring a Sr. RTL Design Engineer - Wireless Modem within a high performance ASIC design ... C and DPI-C. . Ensure that the block meets DFT , timing and power targets by working closely with...architects and system engineers to drive hardware micro-architecture. - Lead design of 1 or more DSP… more
    Amazon (01/05/26)
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  • Principal Digital Engineer

    Renesas (San Jose, CA)
    … and verification + Hands-on knowledge and good experience with Synthesis, Timing Check, and DFT design + Must have experience in developing digital design ... IP, volatile/non-volatile memory IP selection, partitioning of hardware/firmware, RTL design , verification, FPGA prototyping, DFT , and IC...Firmware development experience + Language fluency in Mandarin + Design Lead or Project Lead more
    Renesas (12/23/25)
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  • Optomechanical Design Engineer V

    Applied Materials (Santa Clara, CA)
    …capable international team to develop advanced photonics packaging solution. You will lead optomechanical design , optical sub-assembly design , micro optics, ... new chip and advanced display in the world. We design , build and service cutting-edge equipment that helps our...and operations personnel to develop solutions that adhere to DFT and DFM requirements. Successful Candidates For This Position… more
    Applied Materials (01/08/26)
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  • Sr. ASIC Design Engineer

    Amazon (Sunnyvale, CA)
    …Synthesis, Lint (RTL, DFT , UPF), Power Analysis and STA -Take the lead and work with verification teams to define functional coverage -Work with pre-silicon ... power, performance, and area for significant IPs early in design cycle -Execute on design specifications to...on testplans -Write high quality documents to guide and lead a scalable team Basic Qualifications -Bachelor's degree in… more
    Amazon (10/18/25)
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  • Test Development Engineer

    Cisco (San Jose, CA)
    …success of our optical transceiver products. As an ATE Test Development Engineer , you'll work closely with cross-functional teams-including design , product ... our customers worldwide. **Your Impact** As an ATE Test Engineer , you will play a key role in ensuring...transceiver products at wafer and CoCoS levels. + Influence NPI/ design phases to optimize DFT /DFM, test coverage,… more
    Cisco (01/07/26)
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  • Hardware Application Engineer - SoC Product

    NVIDIA (Santa Clara, CA)
    …escalations, and complex design challenges. + Support product design reviews-offering recommendations, DFM/ DFT improvements, and risk mitigation strategies ... We are seeking a skilled Hardware Application Engineer to provide complete SoC product and platform support across the full hardware lifecycle. In this role, you… more
    NVIDIA (01/10/26)
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  • ATE Test Engineer - EAG Laboratories

    Eurofins US Network (Santa Clara, CA)
    …"Green Card Holder"), Political Asylee, or Refugee._ Key Responsibilities: + Lead cross-functional test development initiatives, collaborating with design , ... every day. We are looking for a ATE Test Engineer with proven experience in developing and supporting complex...and implement ATE programs and own the product from design , initial samples all the way through high volume… more
    Eurofins US Network (01/07/26)
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  • Senior Failure Analysis Engineer

    NVIDIA (Santa Clara, CA)
    …impact on the world. We are seeking a highly skilled and motivated FA engineer to join us. You will play a leading role developing Chip-Debug and Fault-Isolation ... and work closely with our test HW group, mechanical design and tool vendors. What You'll Be Doing: + Lead the enablement of XADA and existing NIR and Thermal… more
    NVIDIA (01/10/26)
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  • Application Engineer Architect

    Cadence Design Systems, Inc. (San Jose, CA)
    …innovating for the most advanced companies in the world. Through Cadence's Electronic Design Automation (EDA) products, we've worked with a wide range of customers, ... in Synthesis, P&R, and Signoff to meet/exceed their PPA targets, achieve faster design closure, and turn their design concepts into reality. The greater… more
    Cadence Design Systems, Inc. (12/09/25)
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  • Senior Custom ASIC Engineering Lead

    Broadcom (San Jose, CA)
    … capable of leading external and internal cross-functional teams in areas such as physical design , STA, DFT , and packaging? Have you taped out so many chips that ... Our ASIC products division is looking for a senior engineer to guide Customer teams designing challenging chips in...design verification, DRC, logic synthesis + Knowledge of DFT methods including scan, memory BIST and repair **Education… more
    Broadcom (11/06/25)
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  • ASIC Engineering Technical Leader

    Cisco (San Jose, CA)
    …crafting cutting edge next generation networking chips. **Your Impact** You will be the lead to drive the DFT /DFx and quality process through the early product ... **Key Responsibilities:** + Responsible for development of the comprehensive Design -for-Test ( DFT ) & DFx solutions and architectures...screening, in-system test, debug and diagnostics needs of the design . + Lead the RTL implementation from… more
    Cisco (11/12/25)
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