- Cerebras (Sunnyvale, CA)
- …over 10 times faster than GPU-based hyperscale cloud inference services. About The Role As a lead front-end design engineer , you will be a key part of the ... Wafer Scale Engine (WSE). This role requires deep expertise in RTL design and integration, with a strong focus on delivering high-performance, power-efficient,… more
- Advanced Micro Devices (Santa Clara, CA)
- …The ideal candidate will have a proven track record in creating scalable digital microarchitectures and will work closely with various teams to ensure the successful ... delivery of complex SoCs. Candidates must possess excellent leadership, communication, and collaboration skills. A background in computer engineering or electrical engineering is preferred. #J-18808-Ljbffr more
- Theconstructsim (Milpitas, CA)
- A semiconductor solutions company based in Milpitas, CA, is seeking a Sr Design Verification Engineer to oversee verification methodologies and collaborate with ... design teams to ensure compliance with project specifications. The ideal candidate will possess a BS/MS in Computer Science or Electrical Engineering and have 5-10+ years of experience in high volume IC production, including strong UVM capabilities and… more
- Altera (San Jose, CA)
- …on our journey to becoming the world's #1 FPGA company!**About the Role**As a Sr. Physical Design Tech Lead / Engineer at Altera, you will play a critical role ... logic blocks, routing fabrics, I/O rings, on-chip power domains).**Key Responsibilities** Lead and execute physical design implementation tasks (floorplanning,… more
- Cadence Design Systems (San Jose, CA)
- Lead Applications Engineer DDR Design IP page is loaded## Lead Applications Engineer DDR Design IPlocations: SAN JOSEtime type: Full timeposted ... matter where you are in your career. As a Lead Technical Presales Engineer , you will use...definers and designers Write application notes, user guides, articles, design ideas, new product proposals, and evaluation kit manuscripts… more
- Analog Group (San Jose, CA)
- The Sr. Digital Design Engineer candidate must have demonstrated success in digital design & verification/infrastructure development for digital FPGAs/ASICs. ... Other key skills include technical/project leadership, documentation, RTL design knowledge, backend flow and tools...flow and tools knowledge. Candidate will be expected to lead designer, verification, and be technical focus on one… more
- Credo Semiconductor, Inc. (San Jose, CA)
- …technologies - because at Credo, We Connect. About the Role As a Senior Physical Design Engineer , you will manage all aspects of physical design and ... PD/integration teams in China and Taiwan to ensure successful tapeouts. Responsibilities Lead and drive top-level, IP, and block-level physical implementation from … more
- Encore Semi Llc (San Jose, CA)
- Sr Physical Design Engineer (Remote) Full-time: Salary + Benefits + Bonuses / Contractor Work Status: US citizen or Lawful Permanent Resident. Remote (Anywhere ... in US) Responsibilities Lead full-chip and block-level physical design for...routing of critical paths. Establish, improve, and scale physical design methodologies, automation, and RTL -to-GDS flows. Provide… more
- Cadence Design Systems (San Jose, CA)
- Senior Principal Emulation Design Engineer page is loaded## Senior Principal Emulation Design Engineerlocations: SAN JOSEtime type: Full timeposted on: ... on the world of technology.**We are seeking a highly skilled** Design Engineer ** to join our Palladium Solutions...configuration, control and status monitoring.** + **SystemVerilog** for synthesizable RTL design + **C and Python** for… more
- Altera (San Jose, CA)
- Altera .Timing Engineer / Lead page is loaded## Timing Engineer /Leadlocations: San Jose, California, United Statestime type: Full timeposted on: Posted ... FPGA company!**About the Role**Altera is looking for a Timing Engineer to lead timing activities for a...usage.* Generate and validate timing ECOs, partnering with physical design and RTL teams for quick closure.*… more
- Altera (San Jose, CA)
- …Details:** ## **Job Description: Job Summary:**Altera is seeking a passionate and driven engineer to join our Design Automation team, focusing on developing and ... clock tree synthesis (CTS), routing, and signoff.* Develop and maintain end-to-end design automation flows for RTL -to-GDSII implementation.* Create and optimize… more
- Renesas Electronics Corporation (San Jose, CA)
- …MCU, peripheral IP, volatile/non-volatile memory IP selection, partitioning of hardware/firmware, RTL design , verification, FPGA prototyping, DFT, and IC ... on-chip bus system, DMA and interrupt system Digital IP RTL design , simulation, and release Independently handle...Python, etc. Firmware development experience Language fluency in Mandarin Design Lead or Project Lead … more
- Cadence Design Systems (San Jose, CA)
- Sr Principal Product Engineer - Memory IP page is loaded## Sr Principal Product Engineer - Memory IPlocations: SAN JOSEtime type: Full timeposted on: Posted ... world of technology.**Cadence is a pivotal leader in electronic design , building upon more than 30 years of computational...OverviewJoin our growing and dynamic IP team and help lead the proliferation of best-in-class Memory PHY IP products… more
- Lattice (San Jose, CA)
- …Memory DDR(DDR4, LPDDR4, DDR5 etc), DPHY, PLL, DSP, Fabric, I/O etc. As a Silicon Design Validation engineer , you will have an opportunity to learn and train ... certain IP, bench hardware and software. Develop test logic RTL to achieve intended validation/characterization test. Drive new silicon...strong desire to pursue an engineering career in Silicon Design Validation Capability to lead small group… more
- Etched.ai, Inc. (San Jose, CA)
- …boot, initialization, and system-level debug. Diagnose complex silicon issues across RTL , firmware, and hardware layers. Collaborate with design , verification, ... Post-Silicon Validation Engineer About Etched Etched is building AI chips...metrics, and signoff criteria across subsystems. Work cross-functionally with RTL , DFT, ATE, firmware, and architecture teams to ensure… more
- FHLB Des Moines (San Jose, CA)
- Senior Engineer II - Product page is loaded## Senior Engineer II - Productlocations: CA - San Jose - 3850 N. First Sttime type: Full timeposted on: Posted ... Yesterdayjob requisition id: R1562-25People come to work at Microchip because we help design the technology that runs the world. They stay because our culture… more
- IBM Computing (San Jose, CA)
- …in various aspects of the development, test, and support process, such as: Logic ( RTL ) design and verification, physical design , and analog/IO design ... a job - it's a calling: To build. To design . To code. To consult. To think along with...things you've never thought possible. Are you ready to lead in this new era of technology and solve… more
- Advanced Micro Devices (Santa Clara, CA)
- …AMD. KEY RESPONSIBILITIES Technical Microarchitecture lead on AMD Data Fabric RTL design team focused on driving the best scalability, modularity, power, ... In this role the candidate will work with IP and SOC Architecture team, RTL design team, verification team, and physical design team to drive the … more
- Intel Corporation (Santa Clara, CA)
- …seeking a Senior Design Engineer - AI SoC Development in California to lead logic design and RTL coding for cutting-edge AI applications. The ideal ... candidate will have over 7 years of experience in ASIC/SoC development, strong technical skills, and a collaborative mindset. Responsibilities include defining architecture, optimizing designs for performance and power, and mentoring junior engineers. This… more
- Advanced Micro Devices (San Jose, CA)
- …and beyond. Together, we advance your career. THE ROLE: We are seeking an engineer with strong hands‑on experience in FPGA build flows, design qualification, and ... unified infrastructure, and ensure continuous quality and reliability of FPGA based platform design flows at scale. This role sits at the intersection of FPGA… more
