- Advanced Micro Devices, Inc (San Jose, CA)
- …AMD together we advance_ THE ROLE: AMD is seeking a ASIC Design Engineer with specific experience with scripting skills around the EDA tool environments to ... flow which performs implementation of RTL through pre-netlist synthesis and static timing analysis. He/She will also develop parsers to extract and waive key… more
- Microsoft Corporation (San Jose, CA)
- …optimize the Cloud infrastructure. We are looking for a **Principal Timing /STA Engineer ** to join the team. **Responsibilities** + Lead the STA ... methodology development and execution to meet timing closure targets for complex semiconductor designs. + Collaborate...implementation, and physical design teams to define and drive timing constraints and methodology . + Conduct … more
- NVIDIA (Santa Clara, CA)
- …complex challenges across diverse industries. NVIDIA Silicon Solutions Group is seeking a versatile engineer to be part of the HW ArchDev team. The SSG team is ... + Build supporting tools/script/infrastructure with relevant stakeholder teams. + Lead post-silicon bringup and support debug activities. + Continuously optimize… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …who want to make an impact on the world of technology. Job Title: Lead Application Engineer Location: Tampere, Finland Reports to: AE Director Job Overview: ... Logical Equivalency Checking (LEC), Design-for-Test (DFT), Place & Route and Static Timing Analysis (STA).You may get involved in design services projects and/or… more
- NVIDIA (Santa Clara, CA)
- …Productization, DFP for short, is a group within SSG with focus on SOL methodology , design, testplan and tools to efficiently enable, test and deploy new chip ... DFP team is looking for a Speed and Reliability Lead . You will be leading and crafting testability features...be leading and crafting testability features related to Speed, Timing and Reliability from ground up as you help… more
- Cisco (San Jose, CA)
- …functional verification **Preferred Qualification:** + DFT CAD development - Test Architecture, Methodology and Infrastructure + Test Static Timing Analysis + ... Senior DFx/RTL Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1447271) + Location:San Jose, California, US...Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus… more
- Broadcom (San Jose, CA)
- …including synthesis, design for test, floorplanning, place and route, clock methodology , power planning and analysis, timing closure, signal integrity ... large complex design implementations using the latest technology nodes, lead one or more disciplines in design closure as...results. + Complete tasks with little supervision, able to lead projects and set direction for other project members.… more
- Qualcomm (Santa Clara, CA)
- …to help create a smarter, connected future for all. As a Qualcomm CPU Engineer , you will lead innovative Central Processing Unit (CPU) design efforts that ... Business Units. Minimum Skill/Experience: + 2-10 yrs experience in Physical Design and timing signoff for high speed cores. + Should have good exposure to high… more
- NVIDIA (Santa Clara, CA)
- …feature bring-up plans for new silicon, and participate in bring-up execution. + Lead debug efforts from the HW side to root cause feature sequence bugs, ... EE fundamentals, knowledgeable in digital design, computer architecture, power analysis, timing analysis, fault analysis, sampling, statistics, and scripting. + Deep… more
