- Cornelis Networks, Inc. (San Jose, CA)
- …block- and system-level test plans to ensure comprehensive design coverage. Define timing constraints for RTL blocks and work with Physical Design engineers to ... optimize timing closure. Support post-silicon validation, collaborating with hardware, firmware,...hardware, firmware, and software teams to debug and resolve ASIC issues. Contribute to performance optimization and power-aware design… more
- Broadcom Inc. (San Jose, CA)
- …Account, please Sign-In before you apply.**## **Job Description:**Looking for a design engineer to work on challenging high speed design of complex modules for ... Familiarity with digital chip design concepts, such as clocking, timing , pipelines, and performance vs area/power tradeoffs.**Additional Job Description:… more
- Hewlett Packard Enterprise Development LP (Sunnyvale, CA)
- A leading technology company in Sunnyvale, California, seeks an experienced engineer to join the Physical design team. The role involves optimizing floorplan and ... timing closure while validating designs with the Verification team. Candidates must have a Bachelor's degree in Electrical Engineering and over 10 years of… more
- SQL Pager LLC (San Jose, CA)
- …specification RTL implementation of the specification while meeting power, area, timing constraints Work with Verification team to verify functionality Work with ... Backend team to go through ASIC flow to tape-out success Work with Firmware teams...RTL design, verification, Lint, CDC, LEC, logic synthesis, DFT, timing analysis, floor-planning, GLS, ECO, bring-up & lab debug… more
- Cadence Design Systems (San Jose, CA)
- Senior Applications Engineer - DDR Design IP...IP benchmarking * Run RTL synthesis for area and timing analysis * Present IP demos to customers * Travel ... page is loaded## Senior Applications Engineer - DDR Design IPlocations: SAN JOSEtime type: Full...subsystem verification and/or performance analysis * Strong knowledge of ASIC flow, RTL design in Verilog, System Verilog and… more
- Cadence Design Systems (San Jose, CA)
- …who want to make an impact on the world of technology.**We are looking for SoC/ ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate ... testbenches.Requirements;US citizenship preferred.* Prior 5-15 years of professional experience in SoC/ ASIC Digital Design with focus on Design for Test (DFT)*… more
- Google Inc. (Mountain View, CA)
- Senior Silicon Physical Design Engineer , TPU, Google Cloud Apply Bachelor's degree in Electrical Engineering or equivalent practical experience. 5 years of ... VLSI design in SoC or multiple-cycles of SoC in ASIC design. Experience with layout verification and design rules....or more physical design partitions or top level. Manage timing and power consumption of the design. Contribute to… more
- NVIDIA Corporation (Santa Clara, CA)
- …or any other characteristic protected by law.The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all ... evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL.*… more
- SQL Pager LLC (Sunnyvale, CA)
- Job Responsibilities * To help develop an ASIC for our automotive and Data Center artificial intelligence computing architecture * Participating in Architecture ... years or PhD with 8+ years, 5+ years in ASIC design team lead. * Experience in logic design...System Verilog, C++, Perl/Python, UVM, Synthesis, Formal Verification, Static Timing Analysis * Experience with processor design, AI/Deep Learning,… more
- Google Inc. (Sunnyvale, CA)
- …focus on TPU architecture and its integration within AI/ML‑driven systems. As an ASIC Physical Design Engineer , you will collaborate with RTL, Design for ... including key stages like floorplanning, place and route, and timing closure). Experience in Python, Tcl, or Perl scripting....partners on Physical Design (PD) closure. Experience in Static Timing Analysis (STA), with an understanding of how to… more
- SPACE EXPLORATION TECHNOLOGIES CORP (Sunnyvale, CA)
- …to work extended hours and weekends as needed COMPENSATION & BENEFITS Pay range: ASIC Design Engineer / Senior : $170,000.00 - $230,000.00 per year. Your actual ... ultimate goal of enabling human life on Mars. SR. ASIC DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX...that in top level and deliver the fully verified, synthesis/ timing clean design Work closely with verification team to… more
- Intel Corporation (Santa Clara, CA)
- # **Welcome!**## . Senior Design Engineer - AI SoC Development page is loaded## Senior Design Engineer - AI SoC Developmentlocations: US, California, ... applications, from edge devices to data center accelerators. If you are an engineer with strong technical and communication skills who thrives in a fast-paced… more
- NVIDIA Corporation (Santa Clara, CA)
- Senior Systems Prototyping Engineer page is loaded## Senior Systems Prototyping Engineerlocations: US, CA, Santa Claratime type: Full timeposted on: Posted ... place and route.* Improve performance of the prototype, analyze timing and generate bit streams.* Bring up the design...Protocompiler or Synplify Premier and Xilinx Vivado* Exposure to ASIC design and verification tools (VCS or equivalent, Verdi,… more
- NVIDIA Corporation (Santa Clara, CA)
- We are now looking for a Senior Signal & Power Integrity Engineer !NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... in a dynamic cross-functional role to optimize package, PCB, ASIC , mixed signal circuit.**What we need to see: BS/MS-Electrical...2D such as Ansys2D.* Familiarity with a system level timing or loss budget including silicon, package and board… more
- quadric.io, Inc (Burlingame, CA)
- …to get in on the ground floor of a revolutionary new processor architecture. As a senior member of our chip design team, you will contribute to all stages of the ... SystemVerilog Own Power, Performance & Area (PPA) optimization Contribute to timing closure through full product cycle (front end, back-end, tapeout) Requirements:… more
- Atlas Data Storage, Inc. (San Francisco, CA)
- Staff Software Engineer , Full-Stack & Firmware Atlas Data Storage is charting the future of information storage by pioneering DNA data storage technology. We're a ... long-term data challenges in the world. We're looking for an exceptional Staff Software Engineer to join our core engineering team. This is a unique opportunity to… more
- NVIDIA (Santa Clara, CA)
- …life's work, to amplify human inventiveness and intelligence. We are now looking for a motivated Senior ASIC Timing Engineer to join our dynamic and ... inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs, CPUs, DPUs...DFX, Clocks, and other teams in coming up with timing closure strategy, creating timing constraints, driving… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If ... work, to amplify human inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs, CPUs, DPUs and SoCs at block… more
- Cisco (San Jose, CA)
- **Sr. ASIC Engineer ** The application window is expected to close on 1/26/2026. The job posting may be removed earlier if the position is filled or if a ... service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is looking for a Senior Reset and Boot ASIC Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our ... Make the choice to join us today. With the System- ASIC team, you will contribute to designing multiple products...be responsible for the RTL design, logic synthesis, and timing analysis of several modules. + Integrate modules into… more
