• Senior SoC Power Analysis

    NVIDIA (Santa Clara, CA)
    …of additional relevant work experience focused on computer architecture and SOC power -perf analysis and optimization . + Understanding of the many factors ... We are now looking for a Senior SoC Power Analysis Engineer! NVIDIA is seeking an exceptional silicon power analysis and optimization engineer to… more
    NVIDIA (01/10/26)
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  • Sr. Manager - SoC Virtual Platform…

    Amazon (Cupertino, CA)
    …servers. Our team builds functional models of these SoCs and the servers they power . Our models are used by AWS internal teams for silicon verification and to ... team manager, you will: * Lead the team responsible for developing SoC models end-to-end, including model architecture, integration with other model or… more
    Amazon (12/17/25)
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  • Sr. SOC /ASIC DFT Engineer (Silicon…

    SpaceX (Sunnyvale, CA)
    …engineering field + Extensive experience in post-silicon bringup, including silicon debug, failure analysis , and yield optimization on complex SoCs or ASICs + ... Sr. SOC /ASIC DFT Engineer (Silicon Engineering) Sunnyvale, CA Apply...for testability (eg, IEEE 1500, 1687) and experience with low- power DFT techniques using Siemens Tessent + Experience with… more
    SpaceX (01/11/26)
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  • AR Subsystem Power Architect

    Meta (Sunnyvale, CA)
    …and hardware validation platforms 3. Conduct analysis and optimization of SOC subsystems to achieve optimal power , performance, and area (PPA) targets 4. ... ( SOC ) components and subsystems 2. Lead technical analysis and optimization efforts for SOC...including next-generation applications 13. Experience leading Intellectual Property (IP) power optimization analysis using traffic… more
    Meta (12/20/25)
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  • Datacenter GPU Power Architect

    NVIDIA (Santa Clara, CA)
    …improvements at GPU and Datacenter level. + You will help with Performance vs Power Analysis , track ASIC milestones for impactful NVIDIA future product lineup. + ... + MSEE/MSCE, or equivalent experience with 2+ years of experience related to Power / Performance estimation and optimization techniques. + Knowledge of energy… more
    NVIDIA (11/06/25)
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  • Hardware Power Test Engineer, Platforms

    Google (Sunnyvale, CA)
    power architecture, SoC power architecture, and component-/tray-/rack-level power management and optimization . + Understanding of power testing ... Hardware Power Test Engineer, Platforms _corporate_fare_ Google _place_ Sunnyvale,...languages, eg, Python, for test automation, data collection and analysis . + Knowledge of one or more of the… more
    Google (12/18/25)
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  • Senior GPU Low Power Architect

    NVIDIA (Santa Clara, CA)
    …models for our GPUs, CPUs, Switches, and platforms. + Drive performance vs power analysis to enable management/marketing with meaningful product decisions and ... in the research and development of hyper-efficient GPU and SOC architectures that power AI, Automotive, Graphics,... reduction and CG strategies. + Background with RAM power optimization . + Experience with directed and… more
    NVIDIA (01/10/26)
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  • Senior Silicon and System Product Lead

    NVIDIA (Santa Clara, CA)
    …physics. + Familiarity with silicon bringup and validation, frequency and power characterization, product analysis and optimization ; hands-on ... and quality optimizations and features for the world's fastest power -shipping products in the GPU and SoC ...+ Experience with system level features, product binning methods, optimization techniques, methods and tools for data analysis more
    NVIDIA (01/10/26)
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  • Digital Design Engineer

    Meta (Sunnyvale, CA)
    …Engineering, relevant technical field, or equivalent practical experience 13. Experience with low power design and optimization to help meet the power ... and use your digital design skills to implement and contribute to development and optimization of state of the art graphics algorithms. You will also support the… more
    Meta (12/20/25)
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  • Hardware Application Engineer - High-Speed IO…

    NVIDIA (Santa Clara, CA)
    …roles + Solid understanding of electrical and thermal requirements for high‑ power SoC /GPU/CPU systems. + Excellent communication skills and proven ... + Own LPDDR5X memory support, including initial tuning, validation process, failure analysis , debugging, and system parametric optimization for OEM platforms. +… more
    NVIDIA (01/10/26)
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  • Senior ASIC Design Engineer - DFX

    NVIDIA (Santa Clara, CA)
    …Familiarity with related domains such as clocking, STA, place & route, and power optimization . + Experience in post-silicon bring-up on ATE, including ... design, implementation, and verification of DFT IPs for our next-generation SoC products. You'll help drive innovation across the full silicon lifecycle-from… more
    NVIDIA (01/10/26)
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  • Virtual Platform Engineer

    Capgemini (Santa Clara, CA)
    …software and firmware teams. + Enhance virtual platforms with instrumentation for power , performance, and architectural trade‑off analysis . **Your skills and ... early software enablement and silicon innovation. You will model advanced SoC architecture and collaborate closely with architects, designers, and firmware teams… more
    Capgemini (12/30/25)
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  • Physical Design Engineer, 3D Technology, PhD,…

    Google (Sunnyvale, CA)
    …and optimizations in physical design spaces. + Understanding of standard cells, SRAMs, power , noise, and IR analysis . + Excellent presentation and communication ... team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to...the slowing of Moore's Law while delivering ASIC's and SoC 's. You will help develop new 3D technology physical… more
    Google (12/24/25)
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  • Senior Accelerated Computing Product Manager

    NVIDIA (Santa Clara, CA)
    …their competitive performance positions from various lenses (throughput, power consumption, SoC usage, potential for future optimization ) -- and then stretch ... analysis to inform engineering changes. + Proven understanding of software optimization , profiling, and performance analysis . + Experience in engaging with… more
    NVIDIA (01/10/26)
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  • Sr. Technical Program Manager

    LinkedIn (Mountain View, CA)
    …path schedules. + High-Density Power & Cooling Systems: Advanced power distribution architectures (2N, 2N+1 redundancy), PUE optimization achieving sub-1.15 ... Operations & Engineering: Driving forecasting, budget alignment, and resource optimization to maximize impact across infrastructure, financial, and product… more
    LinkedIn (12/24/25)
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  • Sr. Technical Program Manager

    LinkedIn (Mountain View, CA)
    …path schedules (Greenfield Construction/Build Management). + Experience with advanced power distribution architectures (2N, 2N+1 redundancy), PUE optimization ... Operations & Engineering: Driving forecasting, budget alignment, and resource optimization to maximize impact across infrastructure, financial, and product… more
    LinkedIn (12/21/25)
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  • Design Implementation Engineer

    Broadcom (San Jose, CA)
    …achieve desired PPA metrics. + Complete equivalence checks, STA, Timing closure and power optimization . + Implement timing and functional ECOs. + Apply ... on experience with timing analysis and place and route tools for ASIC/ SoC Design is a must. **Additional Requirements:** + Good problem solver. + Self starter… more
    Broadcom (12/12/25)
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  • EDA Methodology Architect

    NVIDIA (Santa Clara, CA)
    …of industry leading hardware. We achieve distinction through extensive design optimization , including combining the best of external EDA with highly optimized, ... (3nm and below) and high performance GPU, CPU and SoC designs. You should have deep, hands‑on experience across...in key stages such as RTL, DFT, synthesis, placement, optimization , CTS, routing, and signoff. Creativity and self-drive to… more
    NVIDIA (01/10/26)
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  • Staff Hardware Systems Architect

    Google (Mountain View, CA)
    …design of large-scale, high-density server platforms, considering system topology, power distribution, advanced cooling methodologies, and mechanical constraints. + ... system-level decisions for host and server architecture, including motherboard design, power delivery, memory subsystems, and high-speed interconnects + Oversee and… more
    Google (11/21/25)
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  • Staff Systems Engineer - AV Platform

    General Motors (Mountain View, CA)
    …communication bandwidth (Ethernet). + Perform system resource allocation, profiling, and optimization to meet performance, power , latency, and reliability ... and real-time constraints. + Strong expertise in system performance analysis and optimization , including CPU/GPU/NPU architectures, memory hierarchies,… more
    General Motors (10/28/25)
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