- Altera (San Jose, CA)
- Altera . Timing Engineer / Lead page is loaded## Timing Engineer /Leadlocations: San Jose, California, United Statestime type: Full timeposted on: Posted ... to becoming the world's #1 FPGA company!**About the Role**Altera is looking for a Timing Engineer to lead timing activities for a subsystem. This person… more
- Altera (San Jose, CA)
- A leading technology company in San Jose, California, is seeking a Timing Engineer to lead timing activities for subsystems. This role requires extensive ... experience in timing analysis and sign-off, as well as proficiency with...proficiency with scripting languages. The ideal candidate will drive timing closure and collaborate closely with design teams. A… more
- Altera (San Jose, CA)
- …per Watt leadership for every product in our broad portfolio.As a **Silicon Design Engineer (Power Technical Lead )**, you will have the opportunity to drive full ... product development cycle* Low power circuit design, including some analog* Timing sign-off analysis* Power optimization techniques such as profiling, clock-gating,… more
- Analog Devices, Inc. (San Jose, CA)
- …variety of applications and markets.**The Position:**The group is seeking an experienced Principal Engineer to lead and contribute to the development of next ... Principal Engineer , eFPGA Place and Route page is loaded##...the development and support of FPGA backend toolset including timing -driven implementation suite (optimization, place and route, bitstream), reporting… more
- Altera (San Jose, CA)
- …to becoming the world's #1 FPGA company!**About the Role**As a Sr. Physical Design Tech Lead / Engineer at Altera, you will play a critical role in our backend ... blocks, routing fabrics, I/O rings, on-chip power domains).**Key Responsibilities** Lead and execute physical design implementation tasks (floorplanning, power… more
- Cadence Design Systems (San Jose, CA)
- …knowledge of Place and Route, Clock Tree, RC Extraction, and UPF/CPF concepts. Lead Tempus timing signoff campaigns with existing and new customers. Automate ... customer sites. Requirements: 10+ years of experience in Static timing analysis. Ability to lead and execute...experience in Static timing analysis. Ability to lead and execute technical campaigns with internal and external… more
- Credo Semiconductor, Inc. (San Jose, CA)
- …- because at Credo, We Connect. About the Role As a Senior Physical Design Engineer , you will manage all aspects of physical design and implementation for Credo SoC ... teams in China and Taiwan to ensure successful tapeouts. Responsibilities Lead and drive top-level, IP, and block-level physical implementation from RTL… more
- Cadence Design Systems (San Jose, CA)
- Application Engineer Architect page is loaded## Application Engineer Architectlocations: SAN JOSEtime type: Full timeposted on: Posted 2 Days Agojob requisition ... and level up your communication, customer, and sales skills. Key Responsibilities* Lead a team of Application Engineers providing technical support to Cadence… more
- Encore Semi Llc (San Jose, CA)
- Sr Physical Design Engineer (Remote) Full-time: Salary + Benefits + Bonuses / Contractor Work Status: US citizen or Lawful Permanent Resident. Remote (Anywhere in ... US) Responsibilities Lead full-chip and block-level physical design for advanced semiconductor...clock architectures, placement and routing, and chip assembly. Own timing closure, signal integrity, power, noise, yield, and physical… more
- Renesas Electronics Corporation (San Jose, CA)
- …RTL design, simulation, and release Independently handle complicated design tasks or lead /drive multiple development efforts Chip level synthesis, timing check, ... digital design and verification Hands‑on knowledge and good experience with Synthesis, Timing Check, and DFT design Must have experience in developing digital design… more
- eBay Inc. (San Jose, CA)
- …control, routing, and traffic policy enforcement. We are seeking an experienced engineer (10+ years) with deep expertise in the Linux kernel networking stack ... and production observability to lead design and implementation of high-performance data planes and...and NIC telemetry. Experience with time synchronization and precision timing (PTP), clocking, and its impact on networking performance.… more
- Cadence Design Systems (San Jose, CA)
- Sr Principal Design Engineer page is loaded## Sr Principal Design Engineerlocations: SAN JOSEtime type: Full timeposted on: Posted Todayjob requisition id: R52250## ... high-performance memory IP architecture design, owning the IC micro-architecture, timing budget, power analysis platform development.* Proficiency in logic design,… more
- Altera (San Jose, CA)
- Altera .Principal FPGA Compiler Software Engineer page is loaded## Principal FPGA Compiler Software Engineerlocations: San Jose, California, United Statestime type: ... optimization algorithms for our FPGA CAD software tools, including timing -driven analytic placement, detailed placement, partitioning and floorplanning* Developing… more
- Analog Group (San Jose, CA)
- The Sr. Digital Design Engineer candidate must have demonstrated success in digital design & verification/infrastructure development for digital FPGAs/ASICs. Other ... design knowledge, backend flow and tools knowledge. Candidate will be expected to lead designer, verification, and be technical focus on one or more device and/or… more
- Altera (San Jose, CA)
- …modules of the Routing and Retiming engine from device modeling to timing closure to runtimeIdeal candidates exhibit the following behavioral traits:* Intellectual ... performance multi-core software systems* Extensive experience as an architect/technical lead for developing EDA/CAD routing algorithms for FPGAs* Proven leadership… more
- General Motors (Mountain View, CA)
- …production ECU design changes. We are seeking a high-performing Mechanical Design Engineer interested in leading the in-house development of GM electronics design. ... external customers. Responsibilities: Execute mechanical design of ECUs per program timing , leading to successful launch of the product. Design mechanical components… more
- Synopsys, Inc. (San Jose, CA)
- …the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of ... simulations, and eye diagram analysis. Strong knowledge of circuit-level and timing analysis for signal integrity applications and compliance standards. Experience… more
- Advanced Micro Devices (San Jose, CA)
- …beyond. Together, we advance your career. THE ROLE: We are seeking an engineer with strong hands‑on experience in FPGA build flows, design qualification, and ... & Build Flow Own FPGA compile/build flows (synthesis, place & route, timing closure, bitstream generation). Develop and maintain reference FPGA designs for build… more
- Altera (San Jose, CA)
- …## **Job Description: Job Summary:**Altera is seeking a passionate and driven engineer to join our Design Automation team, focusing on developing and enhancing ... ML/AI techniques to improve physical design processes such as placement, routing, timing closure, and power optimization.* Evaluate and integrate new EDA tools and… more
- nEye Systems, Inc. (Santa Clara, CA)
- …data centers enhanced performance, efficiency, and scalability. Role Overview We're seeking a Lead Hardware Engineer to drive the design and development of ... ASIC, and software domains. The ideal candidate is a seasoned, hands‑on engineer who thrives in a fast‑paced startup environment and loves translating complex… more
