- Persimmons, Inc. (San Jose, CA)
- …that balance performance, power, area & schedule Collaborate with physical design teams to ensure RTL quality supports timing closure, power targets, ... impact, we want to talk to you. What You'll Do As a Senior ASIC Design Engineer, you will be responsible for building and verifying the Persimmons Chiplet that… more
- Persimmons Inc. (San Jose, CA)
- …that balance performance, power, area & schedule. Collaborate with Physical Design teams to ensure RTL quality supports timing closure, power targets, ... we want to talk to you. What you'll do: As a Persimmons Senior ASIC Design Engineer, you will be responsible for building and verifying the Persimmons Chiplet… more
- Microchip (San Jose, CA)
- …partnership with different teams within the FPGA business unit spanning architecture, ASIC design , verification, physical implementation, and test ... Senior Technical Staff Engineer - Design for Test Company Description Are you looking...implement the testability features into the combined FPGA and ASIC SOC. The DFT lead will be involved from… more
- Advanced Micro Devices, Inc. (San Jose, CA)
- …a team where communication and teamwork are highly valued. Key Responsibilities As an ASIC Design Engineer, your responsibilities span various aspects of SOC ... are members of the SOC Design - Verification, Emulation, STA, and Physical Design teams Support all front end integration activities (Lint, CDC, Synthesis,… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs, CPUs, DPUs...ECOs including crosstalk and noise analysis. + Expertise in physical design and optimization eg, placement, routing,… more
- NVIDIA (Santa Clara, CA)
- …life's work, to amplify human inventiveness and intelligence. What you'll be doing: + Drive Physical Design and timing analysis and closure of NVIDIA's GPUs, ... and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic...with Static Timing Analysis (STA) + Experience physical design and optimization eg, synthesis, floorplanning,… more
- Cisco (San Jose, CA)
- …teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this ... startup-style team. You'll collaborate with exceptional talent with deep ASIC design and development expertise. As part...oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing… more
- Cisco (San Jose, CA)
- …teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this ... provide. You will work with exceptional talent with vast ASIC design and development expertise. With Cisco...oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated Senior ASIC Physical Design Engineer, Netlisting to join our dynamic and ... logic synthesis, netlist quality checks, etc. + Help in all aspects of physical design , such as driving timing convergence, timing constraints generation… more
- NVIDIA (Santa Clara, CA)
- …CPU team, you'll be a liaison between Logic design and Physical design teams responsible for achieving timing , area, performance and power goals of the ... other related high-performance semiconductor designs. + Physical design expertise including hands-on synthesis experience, timing ...expertise is preferred as is a deep understanding of ASIC design flow including RTL design… more
- NVIDIA (Santa Clara, CA)
- …is a plus. + Experience with all stages in the ASIC design flow including emulation, prototyping, DFT, timing analysis, floor planning, ECO, bringup ... NVIDIA is looking for a Senior ASIC Design Engineer to join our...Subsystem Design team, you will collaborate with architects/ design verification/formal verification/ physical design team… more
- NVIDIA (Santa Clara, CA)
- … closure to innovate and implement new Clocking topologies in RTL. + Collaborate with Physical design and timing team to evaluate Clocking concerns and ... will be architecting the clock domain to satisfy functional, physical and testing design requirements. + Engage...of innovative NVIDIA chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing… more
- NVIDIA (Santa Clara, CA)
- … closure to innovate and implement new Clocking topologies in RTL. + Collaborate with Physical design and timing team to evaluate Clocking concerns and ... will be architecting the clock domain to satisfy functional, physical and testing design requirements. + Engage...of innovative NVIDIA chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing… more
- NVIDIA (Santa Clara, CA)
- …modules. What you'll be doing: + Be an integral part of the System ASIC Design team to help with the Micro-architecture definition for system-level functions, ... controllers. + You will be responsible for the RTL design , logic synthesis, and timing analysis of...functions like Reset or Chip Boot + Solid frontend ASIC design skills, including RTL design… more
- Palo Alto Networks (Santa Clara, CA)
- …scenarios, close coverage, and add design -for-debug features. + **Partner** with physical - design teams: review synthesis/ timing reports, rewrite RTL to ... CE, or CS (MSEE or equivalent military experience preferred). + 10+ years' front-end ASIC design ownership, shipping 2+ chips to mass production. + Solid… more
- NVIDIA (Santa Clara, CA)
- …+ A deep understanding of ASIC design flows including RTL design , verification, logic synthesis and timing analysis. + Strong interpersonal skills and an ... We are looking for a Senior ASIC Design Engineer to join our.... + Collaborate with architects, verification engineers, formal engineers, physical design engineers, and software engineers to… more
- NVIDIA (Santa Clara, CA)
- …with all stages of ASIC design flow including front end design and verification, DFT, and timing analysis + Strong team player with outstanding ... We are now looking for a motivated Senior ASIC Design Engineer to join our..., Verilog and/or System-Verilog with a deep understanding of physical design and VLSI + Experience with… more
- Cisco (San Jose, CA)
- …in interactive and waveform debug skills **Preferred Qualifications:** + Experience with RTL Design + Familiarity with ASIC /SoC design flow including ... Cisco's silicon team provides an outstanding, unique experience for ASIC engineers by combining the resources offered by a...verification and coverage for complex chips. You will also design RTL as per the architecture specs. Your collaboration… more
- NVIDIA (Santa Clara, CA)
- By submitting your resume, you're expressing interest in one of our 202 6 Hardware ASIC Design Internships. We'll review resumes on an ongoing basis, and a ... Power and Noise Analysis, Silicon Instrumentation and Measurement + CAD and Physical Design Methodologies (Flow and Tool s Development), Chop Floorplan,… more
- Broadcom (San Jose, CA)
- …clock methodology, power planning and analysis, timing closure, signal integrity and physical design checks. + Participate in large complex design ... Candidate Account, please Sign-In before you apply.** **Job Description:** ASIC Implementation Engineer with demonstrated expertise in multiple disciplines including… more
