- Intel (San Jose, CA)
- …ensure our silicon products meet the highest quality standards for high-volume manufacturing. As a Senior DFT Design Engineer , you will be responsible ... Overview We are seeking a senior skilled DFT Design Engineer to develop and implement comprehensive Design for Test solutions across our… more
- Intel (San Jose, CA)
- A leading semiconductor company in California is seeking a Senior DFT Design Engineer to develop and optimize comprehensive Design for Test ... ensure product quality and innovative testing solutions, while leveraging expertise in DFT methodologies such as SCAN, MBIST, and BSCAN implementations. The ideal… more
- Microchip (San Jose, CA)
- Senior Technical Staff Engineer - Design for Test Company Description Are you looking for a unique opportunity to be a part of something great? Want to join ... during test and quantifying full chip test coverage. Establish and maintain DFT design and insertion guidelines and documents best practices for all development… more
- Altera (San Jose, CA)
- …us in our journey to becoming the world's #1 FPGA company!Altera is seeking a ** Senior Design Automation Engineer ** to join our Design Methodology ... maintaining the core automation infrastructure that supports Altera's FPGA design flows-from RTL to GDSII. In this senior... design methodologies spanning Front-End, handoff to Backend, Design Verification, Design -For-Test ( DFT ), … more
- Vivid Technology (San Jose, CA)
- …quality standards (FuSa, AEC‑Q100, ISO 26262) Support synthesis, STA, clock‑domain crossing, low‑power design , and DFT with physical design teams Ensure ... technology. Key Qualifications 10+ years hands‑on experience in digital design with the understanding of analog and mixed‑signal IC... with the understanding of analog and mixed‑signal IC design , ideally in CMOS technologies at 28nm TSMC Expertise… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test ( DFT ). An intimate knowledge and experience in scan chain insertion, ... of professional experience in SoC/ASIC Digital Design with focus on Design for Test ( DFT ) + Should possess intimate knowledge of DFT insertion flows +… more
- NVIDIA (Santa Clara, CA)
- …with 5+ years, MSEE with 3+ years, or PhD with 2+ years of experience in DFT , system architecture, or RTL design . + Understanding of fundamental DFT topics, ... Excellent understanding of MBIST and IOBIST fundamentals. + Experience in architecting DFT access mechanisms in 3D stacked and dielet/chiplet based designs, and UCIe… more
- NVIDIA (Santa Clara, CA)
- …imagination and intelligence. Make the choice to join us today. Design -for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative ... solutions for DFT architecture, verification and post-silicon validation on some of...exposure to cross functional areas including RTL & clocks design , STA, place-n-route and power, to ensure we are… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer - DFX NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... formal verification using JasperGold is a plus. + Deep expertise in DFT design , methodology, and implementation. + Familiarity with related domains such as… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior ASIC Design Engineer to join our dynamic and growing team in our Circuit Solutions Group! NVIDIA has continuously ... expectations. + Work with front-end teams to overlook correctness of the design (Lint/NA/CDC/Synthesis/ DFT /LEC/STA) + Partner and work with back-end team until… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is looking for a Senior ASIC Design Engineer to join our Memory Subsystem Team! As a Senior ASIC Design engineer at NVIDIA, you'll join a ... to see: + MS/Phd in Electrical Engineering or Computer Engineer or related degree (or equivalent experience). + 5+...plus. + Experience with all stages in the ASIC design flow including emulation, prototyping, DFT , timing… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is looking for a Senior SOC Design Engineer to join our SOC Design team! At NVIDIA, you'll collaborate with brilliant minds to build cutting-edge ... that power everything from AI to gaming! As a Senior SOC Design Engineer , you'll...partnering with experts in ASIC design , Physical design , CAD, Package Design , Software, DFT… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... including crosstalk and noise analysis. + Expertise in physical design and optimization eg, placement, routing, cell sizing, buffering,...or Network processor implementation or SOCs. + Understanding of DFT logic and experience with DFT timing… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior Circuit Design Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting ... synthesis and verification, knowledge of Place and Route, and understanding of Design -for-test ( DFT ) is a plus. + Proficiency in scripting language, such as,… more
- NVIDIA (Santa Clara, CA)
- We are now looking for an ASIC Design Engineer . NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world's leading SoC's ... is required. + Understanding of ASIC design flow including RTL design , verification, logic synthesis, prototyping, DFT , timing analysis, floor-planning, ECO,… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated Senior ASIC Physical Design Engineer , Netlisting to join our dynamic ... What you'll be doing: + You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at...hands-on debugging capability and problem-solving skills. + Background in DFT timing closure for various modes eg scan shift… more
- NVIDIA (Santa Clara, CA)
- …the choice to join us today. The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU and ... CPU clocking. The team collaborates with the front design team to understand the clocking requirements for the...to GPU, CPU and SOC verification team, timing and DFT teams. + Get involved in end-to-end cycle of… more
- NVIDIA (Santa Clara, CA)
- …preferred as is a deep understanding of ASIC design flow including RTL design and verification, DFT , and ECO. + Strong communication and interpersonal skills ... As a member of our CPU Cache Coherent Interconnects Design Team, you will be responsible for the physical... Team, you will be responsible for the physical design of CPU on-chip interconnect network and last-level caches,… more
- NVIDIA (Santa Clara, CA)
- …make a lasting impact on the world. We are now looking for a motivated Senior Timing Closure Engineer to join our dynamic and growing Circuit Solutions Group! ... What you'll be doing: + Participate in groundbreaking processor design in deep submicron technologies. + Work as part...timing closure strategy, timing constraints, timing and power convergence, DFT , as well as ECO implementation. What we need… more
- NVIDIA (Santa Clara, CA)
- …debugging + Actively participate in cross function team including Product Development Engineering, DFT , and IC design to efficiently debug any product failures ... are looking for a creative and experienced ATE Test Engineer . NVIDIA has continuously reinvented itself over three decades....will help transfer GPU gaming and compute products from design engineering to mass production. You will be exposed… more
