- Cadence Design Systems, Inc. (San Jose, CA)
- …on memory subsystem verification and/or performance analysis* Strong knowledge of ASIC flow, RTL design in Verilog, System Verilog and FPGA design * ... to make an impact on the world of technology. Senior Applications Engineer - DDR Design IPJob...IPs and DDR protocols* Work closely with IP Sales staff , marketing and R&D teams to win opportunities* Run… more
- Cisco (Milpitas, CA)
- …features. **Your Impact** We are seeking a highly experienced and accomplished FPGA Senior Design Engineer to provide technical leadership and deep expertise in ... Take ownership of complex FPGA sub-modules, from micro-architecture definition to RTL implementation using Verilog/SystemVerilog or VHDL. + Design &… more
- Oracle (Santa Clara, CA)
- … communities and audiences, consisting of varied roles and responsibilities (eg, architects, senior designers, junior design staff , technicians, etc.). + ... firmware. + FPGA implementation experience. Use of FPGAs in a hardware design context, and/or RTL /gateware implementation. \#LI-SM18 Disclaimer: **Certain US… more