- Meta (Trenton, NJ)
- **Summary:** Meta is hiring ASIC Formal Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Formal Verification Responsibilities: 1. Provide… more
- L3Harris (Camden, NJ)
- …land, sea and cyber domains in the interest of national security. Job Title: ASIC /FPGA Design Engineer (SMES) Job Code: 29446 Job Location: Camden, NJ Schedule: ... Preferred. + 5+ year's equivalent experience developing, implementing, and verification of high-performance communications/networking ASIC /FPGA products. +… more
- Broadcom (Allentown, PA)
- …closure. Additionally, the candidate could be required to do block-level synthesis, verification (static, formal ) and place and route related activities. ... / SoC products. Activities include constraints development, constraints verification , deployment of SDF, extracted timing models and timing...IP and SOC design teams to enable block and ASIC level timing closure. + The engineer … more
- Broadcom (Allentown, PA)
- …development, constraints validation, timing analysis and closure. + Experience with formal verification , timing analysis and Eco implementation. + Experience ... clock tree synthesis, route, timing analysis, timing closure, physical verification (LVS/DRC). Should be able to drive tools and...with timing analysis and place and route tools for ASIC / SoC Design is a must. + Should have… more