- Amazon (San Francisco, CA)
- ASIC Test Engineer , Annapurna...working. Key Job Responsibilities Hardware development for probe, final test , system level test . Software ... and training workloads. We are seeking a mid‑career semiconductor test engineer with a background in classic...such a curious mindset and an urge to learn system architecture will greatly benefit you in this role.… more
- Amazon (San Francisco, CA)
- A leading technology company is seeking a mid-career ASIC Test Engineer to work within Annapurna Labs in San Francisco. The role involves hardware and ... software development to improve semiconductor test processes. Successful candidates will possess a Bachelor's degree in Electrical Engineering, and experience with… more
- Eridu Corporation (San Francisco, CA)
- …AI models. Today's AI performance is frequently limited by system -level bottlenecks. Eridu AI delivers multiple industry-first innovations across semiconductors, ... software, and systems to unlock greater GPU utilization, reduce capital and...Position Overview We are hiring multiple positions from Sr. Engineer to Principal Engineer . We are looking… more
- Apple Inc. (San Francisco, CA)
- Power ASIC Validation and Integration Engineer San...you will be expected to develop a high-quality comprehensive ASIC test plan, design ASIC ... Wireless world. Description We are looking for an applications engineer that is highly motivated to develop and integrate...You will also be responsible for supporting FW teams, silicon/ system architecture/design teams, and factory test teams… more
- Eridu Corporation (San Francisco, CA)
- …and integrate diagnostics into BSPs and BMC firmware for pre‑boot testing and system monitoring. Collaborate with ASIC teams to validate interfaces and protocols ... system engineering teams with diagnostic tools and procedures for production test . Qualifications Support manufacturing and system engineering teams with… more
- Eridu Corporation (San Francisco, CA)
- … System Verilog, OVM/VMM/UVM) with a strong understanding of ASIC Design and Verification flow. Experience with functional coverage, gate/timing/power ... AI models. Today's AI performance is frequently limited by system -level bottlenecks. Eridu AI delivers multiple industry-first innovations across semiconductors,… more
- Eridu Corporation (San Francisco, CA)
- …AI models. Today's AI performance is frequently limited by system -level bottlenecks. Eridu AI delivers multiple industry-first innovations across semiconductors, ... software, and systems to unlock greater GPU utilization, reduce capital and...contact lens). Position Overview We are seeking an RTL Engineer to help define and implement our industry‑leading Networking… more
- Quix Recruitment Group Ltd (San Francisco, CA)
- …devices globally, delivering cutting‑edge performance, efficiency, and functionality across complex hardware systems . They are seeking an RTL Design Engineer to ... verification, physical design, and validation teams to deliver next‑generation ASIC /SoC systems . What You'll Do Translate architectural specifications… more
- Eridu Corporation (San Francisco, CA)
- …AI models. Today's AI performance is frequently limited by system ‑level bottlenecks. Eridu AI delivers multiple industry‑first innovations across semiconductors, ... software, and systems to unlock greater GPU utilization, reduce capital and...We are seeking a highly skilled and motivated Emulation Engineer to join our hardware development team. The ideal… more
- Eridu Corporation (San Francisco, CA)
- …AI models. Today's AI performance is frequently limited by system -level bottlenecks. Eridu AI delivers multiple industry-first innovations across semiconductors, ... software, and systems to unlock greater GPU utilization, reduce capital and...contact lens). Position Overview We are seeking an RTL Engineer to help define and implement our industry-leading Networking… more
- Eridu Corporation (San Francisco, CA)
- …AI models. Today's AI performance is frequently limited by system -level bottlenecks. Eridu AI delivers multiple industry-first innovations across semiconductors, ... software, and systems to unlock greater GPU utilization, reduce capital and...readiness, and block-level debug. Collaborate with Verification to define test plans, PCIe VIP usage, coverage goals, and debug… more
- Renesas Electronics Corporation (San Francisco, CA)
- …digital hand-off and post layout verification. Collaboration with analog engineers and test engineers on analog testability design and debugging. Work closely with ... physical silicon device evaluation where necessary. Qualifications 10+ years of experience in ASIC /IC design with deep knowledge of whole IC design flow from RTL… more
- SQL Pager LLC (San Jose, CA)
- …testbench development, and post silicon bring-up and validation Excellent knowledge of System Verilog and Verilog Experience in developing test benches using ... specifications / architectures / micro-architectures Define and review verification test plans Develop block level and chip level verification environments… more
- Hewlett Packard Enterprise Development LP (San Jose, CA)
- ASIC Engineer Sr StaffThis role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office.**Who We ... cutting-edge ASICs for next-generation networking platforms. We are looking for a seasoned**Design-for- Test (DFT) Engineer ** to join our team and contribute to… more
- Cadence Design Systems (San Jose, CA)
- A leading electronic design automation company in California seeks an experienced SoC/ ASIC Digital Design Engineer with a strong focus on Design for Test ... expertise in scan chain insertion, compression scan technologies, and automatic test pattern generation (ATPG), along with strong problem-solving skills and the… more
- Cornelis Networks, Inc. (San Jose, CA)
- …System Verilog. Collaborate with verification engineers to create block- and system -level test plans to ensure comprehensive design coverage. Define timing ... HPC datacenters. Our differentiated architecture seamlessly integrates hardware, software and system level technologies to maximize the efficiency of GPU, CPU and… more
- Broadcom Inc. (San Jose, CA)
- …leading semiconductor firm in California is seeking an experienced IC Verification Engineer to architect scalable Testbench environments. The role demands 10+ years ... in verification with proficiency in System Verilog and methodologies like UVM.... Verilog and methodologies like UVM. Candidates will drive test plans and debug regression failures while mentoring junior… more
- Ludwig Computing (Mill Valley, CA)
- …architecture, implementation, verification, and testing , with opportunities to explore ASIC ‑relevant design flows and system ‑level integration in support of ... Ludwig Computing FPGA Engineer - Custom Compute Hardware Mill Valley, CA.Remote.Full time...on FPGAs Opportunity to build skills that bridge into ASIC flows, including RTL quality, test benching,… more
- Cisco Systems (San Jose, CA)
- …to high volume manufacturing. Creative Hardware Engineering positions are available in: ASIC Design and Verification System /Board Design Circuit Board Layout ... Hardware Automation Validation and Test Signal Integrity Power Design Minimum Qualifications Currently enrolled...Familiarity with high-speed signal integrity, power electronics, or embedded system design. Knowledge of FPGA/ ASIC design flow… more
- Cisco Systems (San Jose, CA)
- …to large volume manufacturing. Creative Hardware Engineering positions available in: ASIC Design and Verification System /Board Design Circuit Board Layout ... Hardware Automation, Validation and Test Signal Integrity Power Design Minimum Qualifications Currently enrolled...major Proficient experience in hardware engineering areas such as ASIC Design and Verification, System /Board Design, Circuit… more
