• High Speed RTL Design

    Broadcom (San Jose, CA)
    …If you already have a Candidate Account, please Sign-In before you apply.** **Job Description:** High Speed RTL Design Engineer Qualifications include: + ... or Computer Engineering with 10+ years of experience in RTL design . + Proficient with Verilog-HDL/System Verilog...understanding of Signal Integrity and Power Integrity modeling for High Speed designs. - Understanding & exposure… more
    Broadcom (05/08/25)
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  • CPU Cache Subsystem Design Manager

    Google (Mountain View, CA)
    …of experience in high -performance CPU, cache subsystem or AI accelerator logic/ RTL design including microarchitecture definition and PPA optimizations. + 6 ... leading and managing teams for modern processor subsystems with high speed , and lower power design... and integration into SoC, emphasizing on microarchitecture and RTL design for the next generation CPU… more
    Google (05/29/25)
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  • CPU Arithmetic Dataflow Design Manager

    Google (Mountain View, CA)
    …of experience in high -performance CPU, cache subsystem or AI accelerator logic/ RTL design including microarchitecture definition and PPA optimizations. + 10 ... leading and managing teams for modern processor subsystems with high speed , lower power design ....teams to define the microarchitecture and schedule in delivering high -quality RTL that meets project goals. You… more
    Google (05/15/25)
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  • IC Design Engineer

    Broadcom (San Jose, CA)
    …EDA tools and Physical design considerations. 3). Thorough knowledge of high - speed Ethernet networking and CPU I/O bus technologies. 3). Excellent knowledge ... be responsible for various key tasks in the areas of uArch and RTL design of cutting-edge network switch/routing Datapath designs. The day-to-day tasks for this… more
    Broadcom (04/18/25)
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  • Senior/Principal Datapath Design Engineer

    Micron Technology, Inc. (San Jose, CA)
    …of proven experience in Datapath design and high - speed circuit design . + Hands-on experience with RTL writing and synthesis. + Knowledge of high ... plans, including placement and routing optimization, to achieve ambitious goals. + Design high - speed Datapath circuits at the block level, model parasitics,… more
    Micron Technology, Inc. (04/25/25)
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  • AE Director, Serdes Design IPs

    Cadence Design Systems, Inc. (San Jose, CA)
    …CXL, UCIe, Ethernet, USB, MIPI, 112G, 56G. . Familiarity with state-of-the-art SoC design implementation: RTL design , synthesis and static timing analysis, ... The ideal candidate for this position is a seasoned High - Speed Interface Technologist who enjoys leading a...role. It is perfect for someone who has System/ASIC/SoC design experience and great interpersonal and communication skills and… more
    Cadence Design Systems, Inc. (06/04/25)
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  • Design Engineering Director

    Cadence Design Systems, Inc. (San Jose, CA)
    … Printed circuit boards in Schematic and layout level. Familiarity with peripheral chips, high speed interface design techniques, Signal and Power integrity ... to make an impact on the world of technology. Design Engineering Director -HPP The role will be a...Layer and Protocol layer experience on AT LEAST ONE High speed SERDES on Ethernet/ PCIe/CXL/UCIe/ *… more
    Cadence Design Systems, Inc. (04/09/25)
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  • Design Verification Engineer, Silicon

    Google (Mountain View, CA)
    …+ 4 years of experience verifying digital logic at Register-Transfer Level ( RTL ) using SystemVerilog for ASICs or FPGAs. + Experience verifying digital Intellectual ... Property (IP) and subsystems. + Experience in Design Verification (DV) Testbenches/Environments. Preferred qualifications: + Master's degree or PhD in Electrical… more
    Google (05/30/25)
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  • Program Manager (Silicon One) - Software

    Cisco (San Jose, CA)
    …one roof. Our devices are crafted for universal adaptability, delivering high speed without sacrificing programmability, buffering, power efficiency, scale, ... markets, designed for fixed and modular platforms. Our devices deliver high speed without sacrificing programmability, buffering, power efficiency, scale… more
    Cisco (04/17/25)
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  • Silicon Verification Engineer 1

    ManpowerGroup (Mountain View, CA)
    …* Purpose of the Team: The purpose of this team is IP verification to verify the design of high speed interface connecting different parts of an SOC chip. * ... coverage, and other verification collateral * Run tests on RTL and Gate Level Netlists, debug failures to root...moment. They will be working on Certus interfaces and high - speed serial interfaces (CRDAS) for several projects… more
    ManpowerGroup (05/22/25)
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  • ASIC DFT Product Lead

    Cisco (San Jose, CA)
    …experience with full chip DFT architecture, hierarchical testing, and high speed interface tests Preferred Qualifications: * Verilog design experience - ... hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various… more
    Cisco (05/14/25)
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