• STA Engineer (eInfochips Inc)

    Arrow Electronics (San Jose, CA)
    **Position:** STA Engineer (eInfochips Inc) **Job Description:** **Position: STA Engineer (eInfochips Inc)** **Location: San Jose CA (Day-1 Onsite)** ... + Experience in **Static Timing Analysis** and prior working experience with STA tools like **PrimeTime/Tempus** + Understanding of related digital design concepts… more
    Arrow Electronics (06/06/25)
    - Save Job - Related Jobs - Block Source
  • STA Engineer

    Broadcom (San Jose, CA)
    …please Sign-In before you apply.** **Job Description:** Broadcom is looking for a senior level STA engineer . In this highly visible role you will be working on ... with timing ECO creation and final timing signoff. + Proficiency in using STA tools (eg, PrimeTime, Tempus) and scripting languages (eg, Tcl, Perl). + Proficiency… more
    Broadcom (05/08/25)
    - Save Job - Related Jobs - Block Source
  • ASIC Design Engineer - Design & Timing…

    Cisco (San Jose, CA)
    …of our systems, leveraging the latest technology. We're seeking a talented ASIC engineer with a proven track record in high-performance products, ready to make a ... the boundaries of what's possible! Your Impact You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints,… more
    Cisco (04/19/25)
    - Save Job - Related Jobs - Block Source
  • Hardware Engineer

    ManpowerGroup (San Jose, CA)
    …me know your view on below role and share your resume ,if interested. **Hardware Engineer Mid.** Onsite from day 1 San Jose ,CA Contract (12+ months) What candidate ... Being a member of design team who oversees fullchip STA / SDCs and works with physical design and DFT...in Static Timing Analysis and prior working experience with STA tools like PrimeTime/Tempus * Understanding of related digital… more
    ManpowerGroup (06/07/25)
    - Save Job - Related Jobs - Block Source
  • IC Design Engineer

    Broadcom (San Jose, CA)
    …Candidate Account, please Sign-In before you apply.** **Job Description:** R&D Engineer position available in design and physical implementation of high performance ... design tools for Place&Route, Verilog simulation, DRC/LVS verification, Timing analysis ( STA ), Scripting languages - Tcl?Perl/ Python + Proficiency in UNIX/Linux… more
    Broadcom (05/18/25)
    - Save Job - Related Jobs - Block Source
  • SoC Physical Design Engineer

    Google (Mountain View, CA)
    …+ Experience in high performance synthesis, PnR, sign-off convergence, including STA and sign-off. Preferred qualifications: + Experience with ASIC design flows ... and methodology of Physical design. + Experience in low power design Implementation including UPF/CPF, multi-voltage domains, power gating. + Experience with scripting languages such as TCI, or Perl. + Knowledge of computer architecture, Verilog or… more
    Google (05/16/25)
    - Save Job - Related Jobs - Block Source
  • Senior Principal C++ Software Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …desire and ability to work in a fast-paced startup environment. + Expert in STA , Synthesis or QOR improvement techniques in the FPGA prototyping or EDA field. The ... annual salary range for California is $150,500 to $279,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please… more
    Cadence Design Systems, Inc. (05/12/25)
    - Save Job - Related Jobs - Block Source
  • Phyiscal Design Engineer

    Broadcom (San Jose, CA)
    …standard cells placements/clock tree adjustments/routing to achieve design specs ( STA /IR/EM/LVS/DRC). Good timing analysis and CTS knowledge is required. - ... MSEE/MSCS 6+ years (BSEE/BSCS 8+ years) - Expertise in Cadence Innovus/Atop physical design tools - Experience on Calibre LVS/DRC - Low power, signal integrity experience - Work closely with RTL & DFT designers - Strong TCL/Python scripting knowledge required,… more
    Broadcom (05/03/25)
    - Save Job - Related Jobs - Block Source
  • ASIC Design For Test Engineer - Acacia

    Cisco (San Jose, CA)
    …implement and verify Design For Test. * You will also interact with RTL/PD/ STA /ATE, collaborating with them for a successful tape out. Minimum Qualification: * ... Typically: Bachelors + 7 years of related experience, or Masters +4 years of related experience, or PHD + 1 years of experience in ASIC DFT flows and implementation. * Prior experience implementing scan control logic in RTL * Prior experience with hierarchical… more
    Cisco (03/21/25)
    - Save Job - Related Jobs - Block Source
  • ASIC Engineering Technical Leader - SDC

    Cisco (San Jose, CA)
    …concept to first customer shipments. Your Impact You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, ... including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/ STA tools and scripting for automation, you excel at identifying and… more
    Cisco (05/10/25)
    - Save Job - Related Jobs - Block Source
  • ASIC Design Technical Leader - Design & Timing…

    Cisco (San Jose, CA)
    …concept to first customer shipments Your Impact You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, ... including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/ STA tools and scripting for automation, you excel at identifying and… more
    Cisco (05/02/25)
    - Save Job - Related Jobs - Block Source