- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Formal Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Formal Verification Responsibilities: 1. Provide… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Performance & Package Verification Responsibilities:… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... and Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities:...or more of the following areas along with functional verification - SV Assertions, Formal , Emulation 14.… more
- Meta (Sunnyvale, CA)
- …To apply, click "Apply to Job" online on this web page. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Leverage Design ... towards creating a first-pass silicon success. 5. Furthermore, the ASIC Engineer , Design Verification will...stimulus, checkers, and reference models 18. Block/IP/SoC/full chip level verification 19. Formal property verification … more
- NVIDIA (Santa Clara, CA)
- The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design Verification . The NVIDIA Clocks ... reset logic to various units in SOC and GPU ASIC . The complexity of the clocks and resets design...industry-standard verification flows like SV constraint random verification , UVM, Formal Verification , Coverage… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking a hardworking Senior ASIC Design Verification Engineer to help drive sign-off strategies for world's leading GPUs and SoCs. This position ... silicon correlation. + Own the unit and sub-system level verification of various IPs, create functional test plans, and...as VCS-XA or equivalent tools, Gate Level Simulation or Formal Equivalence domains. + Proficiency in scripting language, such… more
- Amazon (Sunnyvale, CA)
- …in the validation of ASIC implementations in Verilog/SystemVerilog . Run formal verification of complex blocks to ensure functional correctness . Work ... Matlab model : development or DV integration experience - Familiarity with formal verification techniques - Strong written and verbal skills Amazon is an equal… more
- SpaceX (Sunnyvale, CA)
- …of design blocks using Verilog/SystemVerilog + Familiar with UPF (unified power format), formal verification , and DRC rule checking experience + Ability to work ... ASIC /SOC DFT Engineer (Silicon Engineering) Sunnyvale,...weekends as needed COMPENSATION AND BENEFITS: Pay range: Design Verification Engineer /Level I: $130,000.00 - $155,000.00/per year… more
- NVIDIA (Santa Clara, CA)
- …of our Memory Subsystem Design team, you will collaborate with architects/design verification / formal verification /physical design team to deliver a ... NVIDIA is looking for an ASIC Design Engineer to join our Memory Subsystem Team! As an ASIC Design engineer at NVIDIA, you'll join a group of… more
- NVIDIA (Santa Clara, CA)
- We are looking for a Senior ASIC Design Engineer to join our Switch Silicon team. As a Design Engineer at NVIDIA, you'll join a group of hardworking ... a fully verified, synthesis/timing clean design. + Collaborate with architects, verification engineers, formal engineers, physical design engineers, and software… more
- Meta (Sunnyvale, CA)
- …as machine learning, video transcoding and network acceleration. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...Peripheral Subsystems 9. Experience with Synthesis, Timing Closure and Formal Verification Methodology 10. Master's or PhD… more
- NVIDIA (Santa Clara, CA)
- …Strong proficiency in micro-architecture and RTL development using Verilog. + Experience with formal verification using JasperGold is a plus. + Deep expertise in ... We are now looking for a Senior ASIC Design Engineer - DFX NVIDIA...groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's… more
- Meta (Sunnyvale, CA)
- …Peripheral Subsystems or Video Codec designs 12. Synthesis, Timing Closure or Formal Verification Methodology 13. TCL, Python, Perl, or Shell-scripting 14. ... click "Apply to Job" online on this web page. **Required Skills:** ASIC Design Engineer Responsibilities: 1. Responsible for micro-architecture development. 2.… more
- Meta (Sunnyvale, CA)
- …click "Apply to Job" online on this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/physical synthesis using advanced ... at RTL & gate level and identify power reduction opportunities. 4. Run formal verification checks between RTL & gate level netlist and debug aborts, inconclusive… more
- Cisco (San Jose, CA)
- …Cadence). + Experience with Spyglass CDC and glitch analysis. + Experience using Formal Verification : Synopsys Formality and Cadence LEC. + Experience with ... service provider networks. Cisco's silicon team offers a unique experience for ASIC engineers, combining the resources and stability of a large, multi-geography… more
- Amazon (Sunnyvale, CA)
- …-Master's or Ph.D degree in Electrical / Communications Engineering -Exposure to Formal verification -Experience with physical implementation flows Amazon is an ... time to revenue. Innovators will be delighted with our integrated verification /validation environment that is used to perform architectural modeling to post-silicon… more
- NVIDIA (Santa Clara, CA)
- …cycles, this is your place to be. This role specifically requires a skilled ASIC Verification Engineer with expertise in cache coherency protocols and ... NVIDIA is seeking a Senior Custom SOC/IP Verification Engineer to verify the next...UVM, and C++, along with a solid grasp of ASIC verification methodologies. What you'll be doing:… more
- Arrow Electronics (Mountain View, CA)
- **Position:** Design Verification Engineer **Job Description:** Principal Accountabilities * Responsible for architecting Verification Environment for ... ASIC SoC and providing verification support from defining verification plan to...technical specification documents * Implement and maintain integrated end-to-end formal verification flow for the formal… more
- Broadcom (San Jose, CA)
- …and driving verification closure * Hands on experience in CDC check, formal verification , functional coverage, gate level debug and emulation tools * Very ... Science or related degree and 12+ years of proven experience in SoC/ ASIC verification or Master's Degree in Electrical Engineering, Computer Science or related… more