- Meta (Sunnyvale, CA)
- …Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Static Verification Responsibilities: 1. Perform Flat ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our...equivalent practical experience. 9. 5+ years of experience in static verification tools 10. Experience with Lint, Clock Domain… more
- Meta (Sunnyvale, CA)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Timing Responsibilities: 1. Develop Timing ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our...analysis , SI noise analysis 13. Experience with running Static Timing Analysis for full chip using DMSA 14.… more
- SpaceX (Sunnyvale, CA)
- …world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation ). In this role, you will be ... Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering)...Develop/improve physical design methodologies and automation scripts for various implementation steps + Closely collaborate with the ASIC… more
- Meta (Sunnyvale, CA)
- …apply, click "Apply to Job" online on this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/physical synthesis ... Physical Design Execution for Clock Tree Synthesis and Routing optimization 20. 4 Static timing analysis and verification at different PVT corner 21. 5. Timing ECO… more
- Cisco (San Jose, CA)
- …service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon ... breadth of growth opportunities that working in a smaller ASIC team can provide. You will work with exceptional...customer shipments. Your Impact You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding… more
- Meta (Sunnyvale, CA)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure organization....We are looking for individuals with experience in backend implementation from Netlist to GDSII in low power and… more
- Broadcom (San Jose, CA)
- …be challenged and gain valuable experience towards enhancing a successful career in ASIC design. You will involve in engineering implementation spec writing from ... marketing/system requirements, RTL design and verification, synthesis, static timing analysis. You will either be responsible for block and/or chip level design and… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... timing constraints, driving timing and power convergence, as well as ECO implementation + Apply knowledge and experience to improve timing convergence flows working… more
- NVIDIA (Santa Clara, CA)
- …generation of high-performance IPs for CPU, GPU and SOC designs. + Owning static timing analysis and convergence of high-performance designs. + You will be ... timing including setting up timing constraints, timing analysis and closure, ECO implementation , and timing methodologies. + Finding the right tradeoffs and balance… more
- Google (Sunnyvale, CA)
- …AI/ML-driven systems. In this role, you will work on the physical implementation of Application-specific integrated circuits ( ASIC ) using advanced technology ... and timing signoff execution. + Develop, support and execute implementation flows around industry-standard static timing and parasitic extraction… more
- Qualcomm (Santa Clara, CA)
- …transformation to help create a smarter, connected future for all. Qualcomm's SoC Implementation Team is looking for skilled engineers to focus on timing constraints ... for premium-tier chips. This is an excellent opportunity to join the Snapdragon implementation team, which is responsible for SoCs in sub-3nm nodes across mobile,… more
- Broadcom (San Jose, CA)
- …working on initial floor plan. 4). Develop Verilog RTL. logic synthesis, physical implementation constraints, static timing analysis. 5). Work directly with the ... brought some of the most complex and cutting-edge networking ASIC 's and multichip solutions to market over the last...physical implementation team from initial floor planning to final timing… more
- Google (Sunnyvale, CA)
- …clock verification, and signoff. Preferred qualifications: + Experience in ASIC physical design, physical design flows, and methodologies including synthesis, ... place and route, Static Timing Analysis (STA), formal verification, Change Data Capture...unparalleled performance, efficiency, and integration. As a Circuits Design Engineer , Clock Design you will collaborate with the architecture,… more
- Meta (Sunnyvale, CA)
- … Engineer Responsibilities: 1. Develop and own physical design implementation of multi-hierarchy low-power ML Hardware design including physical-aware logic ... and back-end hardware designers to drive the Physical design implementation of ML compute blocks in advanced technology nodes...synthesis, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification… more
- Microsoft Corporation (Santa Clara, CA)
- …the Azure Hardware Systems & Infrastructure group is seeking a Senior Silicon Engineer . You will join our front-end silicon team and be responsible for delivering ... scalable and programmable DPU silicon. As a Senior Silicon Engineer in the Data Processing Unit team you will...with the architecture team to develop a programmable silicon implementation . This position is expected to be highly visible… more