- Meta (Sunnyvale, CA)
- …Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical ... **Summary:** Meta is hiring ASIC Implementation Engineers within our Infrastructure...12. 3+ years of experience as a Front End Synthesis & Integration Engineer 13. Experience with… more
- Meta (Sunnyvale, CA)
- …Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical ... **Summary:** Meta is hiring ASIC Implementation Engineers within our Infrastructure...10. 10+ Years of experience as a Front End Synthesis & Integration Engineer 11. Experience with… more
- Meta (Sunnyvale, CA)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Timing Responsibilities: 1. Develop Timing ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our...16. Experience with SOC Design Integration & Front End Implementation 17. Experience with Front End Synthesis … more
- Amazon (Sunnyvale, CA)
- …Engineering or related field, or equivalent experience. * 7+ years of experience in ASIC implementation , ie, synthesis , STA and working with P&R for ... set up the flow for both logic and physical synthesis flow for various technology nodes. * Work with.../ Communications Engineering. * 10+ years of experience in ASIC implementation . * Experience in leading physical… more
- Meta (Sunnyvale, CA)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Static Verification Responsibilities: 1. ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our...the DFT coverage for Stuck-at faults. 5. Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate… more
- Meta (Sunnyvale, CA)
- …this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/physical synthesis using advanced optimization ... and corresponding reset sequence for RDC. 10. Develop timing constraints for RTL- synthesis and PrimeTime-STA for blocks and top-level including SOC. 11. Analyze… more
- SpaceX (Sunnyvale, CA)
- …world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation ). In this role, you will be ... Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering)...capabilities of the Starlink network. RESPONSIBILITIES: + Perform partition synthesis and physical implementation steps (eg … more
- Palo Alto Networks (Santa Clara, CA)
- …to create an environment where we all win with precision. **Your Career** As a Design engineer on the ASIC team, you will create complex digital logic for our ... area, timing, power, and testability in close collaboration with ASIC physical design engineers + Perform synthesis ...of PCIe or Ethernet standards + Experience with hardware implementation of Search Algorithms + Formal property verification +… more
- Cisco (San Jose, CA)
- …service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon ... breadth of growth opportunities that working in a smaller ASIC team can provide. You will work with exceptional...customer shipments. Your Impact You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding… more
- Meta (Sunnyvale, CA)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure organization....We are looking for individuals with experience in backend implementation from Netlist to GDSII in low power and… more
- Broadcom (San Jose, CA)
- …be challenged and gain valuable experience towards enhancing a successful career in ASIC design. You will involve in engineering implementation spec writing from ... marketing/system requirements, RTL design and verification, synthesis , static timing analysis. You will either be responsible for block and/or chip level design and… more
- Meta (Sunnyvale, CA)
- …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...using Verilog, System Verilog and HLS 4. Lint, CDC, Synthesis , & Power Optimization 5. Soft and hard IP… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is seeking an ASIC Engineer , Design to join our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, and ... expert engineers to build "Green" data center accelerators. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Work on Micro-architecture… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is looking for an ASIC Design Engineer to join our Memory Subsystem Team! As an ASIC Design engineer at NVIDIA, you'll join a group of ... design team, you will be responsible for the micro-architecture and design implementation of Tegra SOC memory subsystem modules. You will collaborate with… more
- Meta (Sunnyvale, CA)
- …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Micro-architecture development. 2. RTL ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...using Verilog, System Verilog and HLS. 3. Lint, CDC, Synthesis , & Power Optimization. 4. Soft and hard IP… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer to join our dynamic and growing team. If ... CPUs and GPUs. + Explore design space, create optimum floorplan, drive synthesis , physical implementation , and timing closure by understanding arch/logic as… more
- Meta (Menlo Park, CA)
- …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration. 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...in test plan development and debug. 5. Collaboration with implementation team to close the design on timing and… more
- Meta (Sunnyvale, CA)
- …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...in test plan development and debug 6. Collaboration with implementation team to close the design on timing and… more
- NVIDIA (Santa Clara, CA)
- …timing including setting up timing constraints, timing analysis and closure, ECO implementation , and timing methodologies. + Finding the right tradeoffs and balance ... MS (or equivalent experience) with 3+ years' experience in ASIC Design and Timing + Hands-on experience in STA...and Timing + Hands-on experience in STA tools, ECO implementation , and timing closure of high-speed designs. + Strong… more
- Amazon (Sunnyvale, CA)
- …RTL - Ensure quality by running and tracking results of front-end tools including: Synthesis , Lint (RTL, DFT, UPF), Power Analysis and STA - Work with pre-silicon ... - 7+ years of experience in digital design - Experience with physical implementation flows Amazon is an equal opportunity employer and does not discriminate on… more