• ASIC Rtl Design

    Google (Sunnyvale, CA)
    …subsystem design architecture and microarchitecture specifications. + Develop SystemVerilog RTL to implement logic for ASIC /SoC products according to ... of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Design Engineer , you will play an important role in designing… more
    Google (05/06/25)
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  • ASIC Rtl Engineer , Annapurna…

    Amazon (Cupertino, CA)
    …for in the United States. In Annapurna Labs we are at the forefront of hardware co- design not just in Amazon Web Services (AWS) but across the industry. The work we ... while also being deeply important to our customers. We design and build every component of our hardware and...the future with us! Responsibilities: * Participate in logic design activities as part of Amazon's machine learning custom… more
    Amazon (03/18/25)
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  • SoC RTL Design Engineer

    Google (Sunnyvale, CA)
    …and control subsystem's design microarchitecture specifications. + Develop SystemVerilog RTL to implement logic for ASIC products according to established ... on computer architecture. + 5 years of experience in ASIC design with 3 years of experience...role, you will join a team working on SoC-level RTL design for our data center accelerators.… more
    Google (04/23/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our ... / flow experience + Fundamental digital design concepts and experience in ASIC design flow including RTL design , verification, logic synthesis and… more
    NVIDIA (03/20/25)
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  • ASIC Implementation Engineer

    Meta (Sunnyvale, CA)
    …Area. 14. Knowledge of front-end and back-end ASIC tools. 15. Experience with RTL design using SystemVerilog or other HDL. 16. Experience managing multiple ... (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1....Synthesis & Integration Engineer 13. Experience with RTL Synthesis and design optimization for Power,… more
    Meta (04/18/25)
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  • ASIC Implementation Engineer

    Meta (Sunnyvale, CA)
    …Area. 12. Knowledge of front-end and back-end ASIC tools. 13. Experience with RTL design using SystemVerilog or other HDL. 14. Experience managing multiple ... (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1....Synthesis & Integration Engineer 11. Experience with RTL Synthesis and design optimization for Power,… more
    Meta (04/16/25)
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  • ASIC Design Engineer

    Amazon (Cupertino, CA)
    …massive scale and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and ... signal routing - As a key member of the ASIC design team, you will implement and...Engineering or related technical field - 5+ years in RTL design for SOC - 5+ years… more
    Amazon (04/23/25)
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  • ASIC Design Engineer - New…

    NVIDIA (Santa Clara, CA)
    …equivalent experience). + Proven knowledge of digital design concepts and experience in ASIC design flow including RTL design , verification, logic ... time to join our team! NVIDIA is seeking outstanding ASIC Design Engineers to design ...Boot controllers. + You will be responsible for the RTL design , logic synthesis, and timing analysis… more
    NVIDIA (04/26/25)
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  • Senior ASIC Design Engineer

    Tarana Wireless (Milpitas, CA)
    This position will challenge you! The Senior ASIC Engineer will work on complex ASIC designs for our point to multipoint wireless products. + Architecture ... and micro-architecture of digital subsystems + RTL design of digital circuits using Verilog...design of digital circuits using Verilog + Frontend design development and integration of large ASIC more
    Tarana Wireless (05/01/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Design Engineer . NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... & bus protocols, interconnect networks and/or caches. + Great understanding of ASIC design flow including RTL design , verification, logic synthesis… more
    NVIDIA (03/12/25)
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  • Sr. SOC/ ASIC Physical Design

    SpaceX (Sunnyvale, CA)
    Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON...drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL / design more
    SpaceX (04/15/25)
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  • Senior ASIC Design Engineer

    Palo Alto Networks (Santa Clara, CA)
    …is to create an environment where we all win with precision. **Your Career** As a Design engineer on the ASIC team, you will create complex digital logic ... close collaboration with the Systems Architecture team + Implement RTL designs in SystemVerilog + Ensure that designs meet...military experience required + Minimum 8 years experience in ASIC design + Demonstrated success in taking… more
    Palo Alto Networks (03/19/25)
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  • ASIC Design Engineer

    Cisco (San Jose, CA)
    …aspects of our systems, leveraging the latest technology. We're seeking a talented ASIC engineer with a proven track record in high-performance products, ready ... of what's possible! Your Impact You are a diligent Design /SDC Engineer with strong analytical skills and...timing modes. * Option to also do block level RTL design or block or top-level IP… more
    Cisco (04/19/25)
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  • Sr. ASIC Design Engineer

    Amazon (Cupertino, CA)
    design quality and making the right trade-offs. Key job responsibilities As an ASIC Design Engineer , you will: * Develop and implement high-performance, ... rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze...area and power-efficient RTL designs to meet project specifications and targets *… more
    Amazon (03/15/25)
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  • ASIC Engineer , Physical…

    Meta (Sunnyvale, CA)
    …efficient System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our...to improve performance and power. 5. Work with the RTL design team to understand partition architecture… more
    Meta (04/22/25)
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  • ASIC Engineer , Design

    Meta (Sunnyvale, CA)
    **Summary:** Meta is seeking an ASIC Engineer , Design to join our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, ... engineers to build "Green" data center accelerators. **Required Skills:** ASIC Engineer , Design Responsibilities: 1....Design Responsibilities: 1. Work on Micro-architecture development and Design / RTL coding 2. Work with design more
    Meta (02/06/25)
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  • ASIC Implementation Engineer

    Meta (Sunnyvale, CA)
    …PLL, etc) 13. Knowledge of front-end ASIC flows 14. Experience with RTL design using SystemVerilog or other HDL. 15. Experience with communicating across ... on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Static Verification Responsibilities: 1. Perform Flat… more
    Meta (04/04/25)
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  • Sr. ASIC Design Verification…

    Qualcomm (Santa Clara, CA)
    …a closely related field is preferred + 5+ years of experience with ASIC design and verification tools, techniques, and methodology **Preferred Qualifications** + ... closely related field + 5+ years of experience with ASIC design and verification tools, techniques, and...and methodology + 5+ years of experience with digital design concepts and RTL languages such as… more
    Qualcomm (04/14/25)
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  • ASIC Engineer , Design

    Meta (Sunnyvale, CA)
    **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. As a Design Verification Engineer , you will be ... teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities:...scratch. 13. Experience debugging fails to the line of RTL , closing out bug fixes, using Verdi or equivalent… more
    Meta (02/12/25)
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  • ASIC Design Engineer

    Google (Mountain View, CA)
    …field, or equivalent practical experience. + 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog ... SystemVerilog. + Experience with logic synthesis techniques to improve RTL code, performance and power as well as low-power... code, performance and power as well as low-power design techniques. + Experience with ARM-based SoCs, interconnects and… more
    Google (04/10/25)
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