- NVIDIA (Santa Clara, CA)
- …This role offers a great opportunity to be at the forefront of compiler verification , ensuring our brand-new technology maintains its premier standard. You ... like GDB, LLDB; ELF and Dwarf Standards. + Previous experience in compiler development, verification /testing, or performance analysis; plus unit-test development… more
- NVIDIA (Santa Clara, CA)
- …of compiler technologies to accelerate deep learning workloads. We are looking for an engineer to work on compiler verification in the AI space. You will ... be doing: In this role you will work closely with deep learning compiler developers to create software infrastructure and applications used to develop, test, and… more
- Google (Sunnyvale, CA)
- …and verification for SoCs. + Experience in silicon bring-up, debug , or validation of DFT features. + Experience with industry-standard test methodologies ... SoC DFT Engineer , Google Cloud _corporate_fare_ Google _place_ Sunnyvale, CA,...10 years of experience in DFT architecture, implementation, and verification for SoCs. + Experience with various fault models… more
- Broadcom (San Jose, CA)
- …APD (ASIC Products Division)'s designs - DFT Architecture, Test insertion and verification , Pattern generation, Coverage improvement, Post silicon debug and ... please Sign-In before you apply.** **Job Description:** **Principal DFT Engineer ** Broadcom's ASIC Product Division is seeking candidates for...+ Experience with Serdes, DDR, PCIE, ENET, CXL IOBIST verification and silicon debug is a plus… more
- SanDisk (Milpitas, CA)
- …you'll be at the center of innovation. We are looking for an experienced Principal Engineer to lead and deliver projects for our Memory Design team. This is a great ... design in NAND Flash memory, focusing on micro architecture, RTL design, verification , logic synthesis, and timing analysis to deliver a design meeting target… more
- SanDisk (Milpitas, CA)
- …you'll be at the center of innovation. We are looking for an experienced Staff Engineer to lead and deliver projects for our Memory Design team. This is a great ... design in NAND Flash memory, focusing on micro architecture, RTL design, verification , logic synthesis, and timing analysis to deliver a design meeting target… more
- SanDisk (Milpitas, CA)
- …DRC/LVS verification . Experienced Cadence and Synopsys digital flow: Fusion compiler , DCG, ICC2, Innovus, PT, StarRC ESSENTIAL DUTIES AND RESPONSIBILITIES: + ... We are looking for an experienced **Digital Physical Design Engineer ** to work whole digital SPR flow from RTL...tree quality and timing. + Routing: be able to debug and analysis timing, routing issue in routeOpt stage,… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …to make an impact on the world of technology. Job Title: Lead Application Engineer Location: Tampere, Finland Reports to: AE Director Job Overview: This Digital IC ... Logical Equivalency Checking + Low Power Design Implementation, SDC Verification + Place and Route + Parasitic Extraction, Timing...4+ years of experience in Synthesis (Genus or Design Compiler ), DFT and Logic Equivalency tools Or Cadence or… more