- NVIDIA (Santa Clara, CA)
- As a Formal Verification Engineer at NVIDIA, you will work in the formal verification team for the industry's leading chips. We are looking for ... of formal methods. The engineer will own the task of formal verification of RTL units for next generation chip designs. This will involve the candidate… more
- Amazon (Cupertino, CA)
- …to deliver high performance at low cost. Key job responsibilities - Develop formal verification plans, implement and verify state-of-the-art IP architectures. - ... & Career Growth Our team is dedicated to supporting new members. We have a broad mix of experience...related field - 7+ years of practical experience with formal verification as IP/Block owner, or equivalent… more
- Google (Mountain View, CA)
- Senior Design Verification Engineer , Silicon _corporate_fare_ Google _place_ Mountain View, CA, USA **Mid** Experience driving progress, solving problems, and ... with an emphasis on computer architecture. + Experience in different verification techniques and methodologies including formal , Gate-Level Simulation, Unified… more
- Arrow Electronics (Mountain View, CA)
- **Position:** Design Verification Engineer **Job Description:** Principal Accountabilities * Responsible for architecting Verification Environment for ASIC ... functional and technical specification documents * Implement and maintain integrated end-to-end formal verification flow for the formal verification… more
- Meta (Sunnyvale, CA)
- …from transistors, through architecture, firmware, and algorithms. **Required Skills:** Design Verification Engineer Responsibilities: 1. Define and implement ... vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips...test benches for block, IP, sub-system, and SoC level verification 2. Develop functional tests based on verification… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior Circuit Verification Engineer to join our dynamic and growing team. Designing RAMs at leading edge process nodes ... of innovative circuits. + Support designer efforts in running formal verification , electronic rule checking, and other...products. + Engaging with industry tool AEs to qualify new tool releases, learn about new tool… more
- Amazon (Cupertino, CA)
- …Electrical or Communications Engineering or a related field - Experience with formal verification techniques including abstraction and end-to-end checking - ... solutions achieve their desired functionality, developing and executing multi-faceted verification /validation plans, and measuring the teams progress towards our… more
- SpaceX (Sunnyvale, CA)
- …of design blocks using Verilog/SystemVerilog + Familiar with UPF (unified power format), formal verification , and DRC rule checking experience + Ability to work ... hours and weekends as needed COMPENSATION AND BENEFITS: Pay range: Design Verification Engineer /Level I: $130,000.00 - $155,000.00/per year Design … more
- NVIDIA (Santa Clara, CA)
- …Strong proficiency in micro-architecture and RTL development using Verilog. + Experience with formal verification using JasperGold is a plus. + Deep expertise in ... We are now looking for a Senior ASIC Design Engineer - DFX NVIDIA has continuously reinvented itself over...a "learning machine" that constantly evolves by adapting to new opportunities that are hard to solve, that only… more
- Amazon (Cupertino, CA)
- …tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) develop flows for synthesis, formal verification , floor planning, bus / pin planning, place and ... rapid integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze new technologies and architectures, while… more
- Lockheed Martin (Sunnyvale, CA)
- …any other are with Lockheed Martin Space** **OVERVIEW:** At the dawn of a new space age, Lockheed Martin is a pioneer, partner, innovator and builder\. Our amazing ... does this role look like?** Lockheed Martin is seeking a dynamic, hardworking Systems Engineer to support our SPP programs\. As a Systems Engineer , you will:… more
- Imperative Care (Campbell, CA)
- Title: Senior R&D Engineer This position is based in our Campbell, California offices. This position is on-site, full-time. Why Imperative Care? Do you want to make ... and launch innovative endovascular/neurovascular products through conceptualization, design development, verification /validation, and manufacturability assessments. This role will deliver ideation… more
- Micron Technology, Inc. (San Jose, CA)
- …large language models (LLMs) for the purpose of automated Silicon design and Design Verification (DV). The engineer is expected to build LLM based EDA workflows ... is searching for a highly experience Data Scientist/GenAI Software Development Engineer within out Central Engineering team (CE)! **About the Department:** The… more
- Imperative Care (Campbell, CA)
- …test methods and associated fixturing/automation to support both explorative, characterization, and formal verification testing of the Company's products. + Your ... Job Title: Senior R&D Test Engineer Location : This position is based in...of devices for concept selection, design optimization, and design verification in close collaboration with the preclinical and design… more
- Google (Mountain View, CA)
- …Level (RTL) coding, function/performance simulation debug and Lint/Clock Domain Crossing (CDC)/ Formal Verification (FV)/Unified Power Format (UPF) checks. + ... RTL Design Engineer , Multimedia and Machine Learning Accelerators _corporate_fare_ Google...create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless,… more
- Amazon (Cupertino, CA)
- …of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and architectures, while ... TAT improvements Work with EDA tool vendors to evaluate new methods, resolve bugs, improve usability. Fine tune cloud...and methodologies including synthesis, place and route, STA, IR, formal and physical verification . - Demonstrated level… more
- Roche (Pleasanton, CA)
- …**The Position** We are seeking a highly motivated Principal System Engineer I to join our End-to-End Solution Integration Chapter supporting Next-Generation ... pipelines. **The Opportunity:** This role is ideal for a systems-minded engineer with direct industry experience in sequencing workflows, strong analytical and… more
- Broadcom (San Jose, CA)
- …closure. Additionally, the candidate could be required to do block-level synthesis, verification (static, formal ) and place and route related activities. ... ASIC / SoC products. Activities include constraints development, constraints verification , deployment of SDF, extracted timing models and timing...enable block and ASIC level timing closure. + The engineer will work with the internal ASIC / SoC… more
- Amazon (Cupertino, CA)
- …physical design flows, and methodologies including synthesis, place and route, STA, formal verification . - Proven track record of delivering metric driven ... our customers' businesses. We are seeking experienced Physical Design Engineer to build the next generation of our cloud...low cost. You'll provide leadership in the application of new technologies to large scale deployments in a continuous… more
- NVIDIA (Santa Clara, CA)
- …using various flows and methodologies including: Static Timing analysis, EM and IR analysis, Formal Verification At NVIDIA, we have been at the forefront of ... We are now looking for a Senior SRAM Engineer ! The Full Custom Macro team at NVIDIA...a "learning machine," constantly evolving and adapting to seize new opportunities. We seek challenges that are not only… more