- Broadcom (San Jose, CA)
- …Sign-In before you apply.** **Job Description:** Broadcom is looking for a senior level STA engineer . In this highly visible role, you will be contributing to ... timing constraints for intricate SoC designs. + Perform static timing analysis ( STA ) using industry-standard tools (eg, PrimeTime, Tempus). + Define and implement… more
- Arrow Electronics (San Jose, CA)
- **Position:** STA Engineer (eInfochips Inc) **Job Description:** **What You'll Be Doing:** + Designing the integrated chips by estimating the die area, floor ... planning, placement of memory, power planning, placement, clock building, routing + Design and development of sign off flows based on product specification, which includes, static timing analysis, IR/EM and physical verification through which design will be… more
- Amazon (Sunnyvale, CA)
- …that is powering the latest generation of Echo devices is looking for a Senior SoC Design- STA Engineer to continue to innovate on behalf of our customers. We are ... development of signoff methodology and corresponding implementation solution * Flow for STA , Crosstalk Delay and Crosstalk Noise analysis for digital ASIC/SoCs. *… more
- Amazon (Sunnyvale, CA)
- …that is powering the latest generation of Echo devices is looking for a Senior SoC Design- STA Engineer to continue to innovate on behalf of our customers. We are ... development of signoff methodology and corresponding implementation solution * Flow for STA , Crosstalk Delay and Crosstalk Noise analysis for digital ASIC/SoCs. *… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …on SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing, Distributed and Concurrent STA flows. . Work efficiently with R&D and customer to enable various ... timing analysis & ECO flows including newer advanced technologies. . Performing timing correlation, tool feature benchmarking, constraints validation, spice analysis on various tech nodes and customer designs. . Work on In-design timing ECO optimizations… more
- SanDisk (Milpitas, CA)
- …forward. **Job Description** We are looking for an experienced **Digital Physical Design Engineer ** to work whole digital SPR flow from RTL to GDS, include ... Synthesis, DFT scan insertion, PNR, STA timing analysis, IRdrop power analysis, DRC/LVS verification. Experienced...and analysis timing, routing issue in routeOpt stage, + ** STA timing analysis** + MMMC timing analysis using PT… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and ... and validate flows for Prime-Time , Prime-Shield and Tempus STA QoR metrics for sign-off flow, and tool for...std cells and custom IPs. + Develop flows/recommendations on STA sign-off to model deep submicron physical effects aging,… more
- NVIDIA (Santa Clara, CA)
- …and intelligence. We are now looking for a motivated Senior ASIC Test Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... or MS (or equivalent experience) with 2+ years' experience in Timing and STA + Hands-on experience in full-chip/sub-chip Static Timing Analysis ( STA ) and… more
- Broadcom (San Jose, CA)
- …Account, please Sign-In before you apply.** **Job Description:** **Principal DFT Engineer ** Broadcom's ASIC Product Division is seeking candidates for a DFT ... metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role...and other I/P DFT integration + Working closely with STA and DI Engineers design closure for test +… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are seeking a highly skilled Timing Methodology Engineer with expertise in asynchronous timing and I/O interface modeling to ... timing constraints, validating IO timing integrity, and enabling scalable STA methodologies across design hierarchies and technology nodes. We're looking… more
- Meta (Sunnyvale, CA)
- **Summary:** We are looking for a Digital Design Engineer to support our Reality Labs Silicon AI Research team. We build research silicon to demonstrate and ... next generation AI and AR solutions.As a Digital Design Engineer (DDE), you will be a key contributor in...(DV) 3. Support back end physical design (PD) through STA and SDCs 4. Develop system tests in C… more
- Amazon (Cupertino, CA)
- …AI services for our customers' businesses. We are seeking experienced Physical Design Engineer to build the next generation of our cloud server platforms. Our ... design, physical design flows, and methodologies including synthesis, place and route, STA , formal verification. - Proven track record of delivering metric driven… more
- Amazon (Cupertino, CA)
- …of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and architectures, while ensuring ... physical design, and methodologies including synthesis, place and route, STA , IR, formal and physical verification. - Demonstrated level...in PD tools such as Innovus, ICC2, Fusion Compiler, STA , and Sign-Off. - Proven track record of delivering… more
- NVIDIA (Santa Clara, CA)
- …methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If you are problem solver and ... in Physical design/Timing. + Experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints generation and management, and timing convergence. +… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... and Timing + Hands-on experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints generation and management, and timing convergence. +… more
- NVIDIA (Santa Clara, CA)
- …a lasting impact on the world! We are currently looking for a Senior Methodology Engineer to develop and support our CAD tooling in our Circuit Solutions Group ! In ... VLSI CAD flows and methodology + Timing closure and STA tool experience required + Good programming skills in...+ Experience with .lib characterization flow or other related STA flows + Enjoy working with multiple levels and… more
- SanDisk (Milpitas, CA)
- …and back-end implementation engineers on physical verification, static timing analysis ( STA ), and tape-out readiness + Apply deep knowledge of design principles ... date of **Dec 2024 - May/June 2025** + Knowledge synthesis, place & route, STA timing analysis and physical verification with EDA CAD tools **Preferred Skills:** +… more
- SpaceX (Sunnyvale, CA)
- Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars is ... with the ultimate goal of enabling human life on Mars. PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets… more
- Arrow Electronics (San Jose, CA)
- **Position:** SDC Engineer (eInfochips Inc) **Job Description:** **Position: SDC Engineer (eInfochips Inc)** **Location: San Jose CA (Day-1 Onsite)** **What ... + Experience in **Static Timing Analysis** and prior working experience with STA tools like **PrimeTime/Tempus** + Understanding of related digital design concepts… more
- Microsoft Corporation (Mountain View, CA)
- …the Cloud infrastructure. We are looking for a **Principal Physical Design Engineer ** with **CPU Core expertise** to join the team. \#SCHIE #CSME \#Siliconjobs ... expertise in timing constraints (functional & DFT), static timing analysis ( STA ), and timing-power optimization. + Communication, collaboration and teamwork skills… more