- Diverse Lynx (Cupertino, CA)
- Title: Implementation, Physical Design Senior Engineer Location: Cupertino, CA Duration: Fulltime Job Description Must Have Technical/Functional Skills *Technical ... CTS, post_route, etc.) on latest nodes. Signoff knowledge is mandatory ( STA , Power analysis, FV, Low power verification, Physical Verification). Quick learner… more
- Microsoft Corporation (Mountain View, CA)
- …will manage and optimize the Cloud infrastructure. We are looking for a **Principal Timing/ STA Engineer ** to join the team. **Responsibilities** + Lead the ... STA methodology development and execution to meet timing closure...with industry trends and emerging technologies to continuously improve STA methodologies and processes. **Qualifications** **Required Qualifications:** + Bachelor's… more
- Arrow Electronics (San Jose, CA)
- **Position:** STA Engineer (eInfochips Inc) **Job Description:** **Position: STA Engineer (eInfochips Inc)** **Location: San Jose, CA/ Longmont, CO ... + Experience in **Static Timing Analysis** and prior working experience with STA tools like **PrimeTime/Tempus** + Understanding of related digital design concepts… more
- Amazon (Sunnyvale, CA)
- …that is powering the latest generation of Echo devices is looking for a Senior SoC Design- STA Engineer to continue to innovate on behalf of our customers. We are ... development of signoff methodology and corresponding implementation solution * Flow for STA , Crosstalk Delay and Crosstalk Noise analysis for digital ASIC/SoCs. *… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …on SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing, Distributed and Concurrent STA flows. . Work efficiently with R&D and customer to enable various ... timing analysis & ECO flows including newer advanced technologies. . Performing timing correlation, tool feature benchmarking, constraints validation, spice analysis on various tech nodes and customer designs. . Work on In-design timing ECO optimizations… more
- Qualcomm (Santa Clara, CA)
- …CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer , you will work with microarchitecture and RTL design team to develop timing ... One of your primary responsibilities will lie in coding scripts used with STA native tools and also useful in enabling CPU timing infrastructure and methodology… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and ... and validate flows for Prime-Time , Prime-Shield and Tempus STA QoR metrics for sign-off flow, and tool for...std cells and custom IPs. + Develop flows/recommendations on STA sign-off to model deep submicron physical effects aging,… more
- Microsoft Corporation (Mountain View, CA)
- …the Cloud infrastructure. We are looking for a **Senior Physical Design Engineer ** to join the team. **Responsibilities** + Accountable for Design-for-Test (DFT) & ... coordination across cross-functional teams, including DFT, RTL/Design/IP, Static Timing Analysis ( STA ), CAD, Architecture, Power & Performance, and both internal and… more
- Meta (Sunnyvale, CA)
- …and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Timing Responsibilities: 1. Develop Timing Constraints for RTL-Synthesis and ... PrimeTime- STA for the blocks and the top-level including SOC....Hierarchical Constraints for Functional & DFT Modes 3. Perform STA for full chip and Physical partition blocks using… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... or MS (or equivalent experience) with 2 years experience in Timing and STA + Hands-on experience in full-chip/sub-chip Static Timing Analysis ( STA ) and… more
- Qualcomm (Santa Clara, CA)
- …to help create a smarter, connected future for all. As a Qualcomm CPU Engineer , you will lead innovative Central Processing Unit (CPU) design efforts that have a ... in leading block level or chip level Physical Design, STA and PDN activities** . + Work independently in...to collaborate and resolve issues wrt constraints validation, verification, STA , Physical design, etc. + Knowledge of low power… more
- Meta (Sunnyvale, CA)
- …and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical Synthesis using advanced ... coverage for Stuck-at faults 7. Develop Timing Constraints for RTL-Synthesis and PrimeTime- STA for the blocks and the top-level including SOC. Analyze the… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are seeking a highly skilled Timing Methodology Engineer with expertise in asynchronous timing and I/O interface modeling to ... timing constraints, validating IO timing integrity, and enabling scalable STA methodologies across design hierarchies and technology nodes. We're looking… more
- Cisco (San Jose, CA)
- ASIC Design Engineer - Design & Timing Constraints Apply (https://jobs.cisco.com/jobs/Login?projectId=1439367) + Location:San Jose, California, US + Area of ... of our systems, leveraging the latest technology. We're seeking a talented ASIC engineer with a proven track record in high-performance products, ready to make a… more
- Meta (Sunnyvale, CA)
- **Summary:** We are looking for a Digital Design Engineer to support our Reality Labs Silicon AI Research team. We build research silicon to demonstrate and ... generation AI and Augmented Reality solutions.As a Digital Design Engineer (DDE), you will be a key contributor in...(DV) 3. Support back end physical design (PD) through STA and SDCs 4. Drive IP/sub-system micro-architecture and RTL… more
- Amazon (Cupertino, CA)
- …AI services for our customers' businesses. We are seeking experienced Physical Design Engineer to build the next generation of our cloud server platforms. Our ... design, physical design flows, and methodologies including synthesis, place and route, STA , formal verification. - Proven track record of delivering metric driven… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... and Timing + Hands-on experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints generation and management, and timing convergence. +… more
- NVIDIA (Santa Clara, CA)
- …methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If you are problem solver and ... in Physical design/Timing. + Experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints generation and management, and timing convergence. +… more
- NVIDIA (Santa Clara, CA)
- …We are seeking an innovative senior timing signoff and constraint methodology engineer to develop pioneering timing sign-off strategies for next-generation GPUs and ... SNPS TCM ) and debug anomalies in timing reports. + Support tapeout-quality STA environments that are scalable, reusable, and validated through both structural and… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Compiler) + Experience with EDA tools in the IC digital implementation & signoff flows ( STA tools) + Strong STA and SDC debugging abilities are required. + Low ... power analysis, Clock design/analysis and hands-on 7/5nm technology node experience a plus. + Automation skills using Perl, Tcl and shell scripting essential + Strong analytical & analysis skills covering digital implementation is critical. + Proven track… more
