- NVIDIA (Santa Clara, CA)
- …impact on the world. We need a creative individual who understand ASIC and SoC test methodology , DFT techniques, NPI and ATE test program development and ... release. The individual will turn the test methodology into ATE test method library. efficient and user friendly TML will improve yield, reduce test … more
- NVIDIA (Santa Clara, CA)
- …can make a lasting impact on the world. We are looking for a motivated CAD Methodology Engineer to join our dynamic and growing team. If you like solving ... part of a diverse team creating NVIDIA's chip design methodology ! We're responsible for the RTL CDC and RDC...vendors. Analyze issues, build solutions or workarounds, and provide test cases to EDA vendors. + Invent new methodologies… more
- Amazon (Sunnyvale, CA)
- …Edge that is powering the latest generation of Echo devices is looking for a Senior Design Verification Engineer to continue to innovate on behalf of our ... role, you will be responsible for defining the verification methodology and implementing the corresponding test plan for sub-systems and the full chip. You will… more
- Palo Alto Networks (Santa Clara, CA)
- …we're not just building products - we're redefining what's possible in cybersecurity. As a Senior Staff SDET Engineer , you'll play a critical role in our mission ... efficiency to boost the testing team's productivity. + Apply a consistent test design methodology when developing testing automation. + Design, develop,… more
- NVIDIA (Santa Clara, CA)
- …and verification methodology is required + Strong ability with SystemVerilog, test planning, coverage closure, and test bench design + Understanding of ... across many NVIDIA teams from software, to architecture, design, methodology , and more. The GPU is used in applications...level testbench, working on directed and random tests and test infrastructure, and contributing to the future direction of… more
- Celestica (San Jose, CA)
- …09 **IC/MGR:** Individual Contributor **Direct/Indirect Indicator:** Indirect **Summary** The Senior Lead Engineer , Software develops, debugs, tests, deploys ... etc.) and complies with the product life cycle development (phase/gate deliverables). The Senior Lead Engineer , Software works in cross functional teams with… more
- Amazon (Los Gatos, CA)
- Description eero is looking for a highly focused Senior QA Engineer to work on critical embedded firmware testing projects that keep our platform running ... grow our existing Python automation framework to expand our test coverage. Key job responsibilities - Black and gray...QA projects and initiatives experience - Knowledge of QA methodology and tools, with demonstrated experience in an QAE… more
- Amazon (Sunnyvale, CA)
- Description As a connetivity QA engineer , you will work on projects in a large range of areas: WIFI/BT/Smart home technologies, OS level tests, test automation, ... staff to conceive, design and develop innovative ideas to test consumer products. In Wireless Connectivity QA team, we...of quality assurance engineering experience - Knowledge of QA methodology and tools, with demonstrated experience in an QAE… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Verification Engineer for our Coherent High Speed Interconnect team! For two decades, we have pioneered visual computing, ... solving the most sophisticated problems in everyday life. As a ASIC Verification Engineer at NVIDIA, you will verify the design and implementation of our innovative… more
- NVIDIA (Santa Clara, CA)
- We're now looking for a Senior Digital Design Verification Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... and intelligence. Make the choice to join our diverse team today! As a Senior Digital Design Verification Engineer at NVIDIA, you'll verify the design and… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …for our customers, our communities, and each other-every day. Key Responsibilities The Senior Principal Design Engineer will define the DFT Architecture for the ... other DFT's related logic. Additionally, they will define and develop methodology for DFT insertion, pattern development, manufacturing tests, verifications, etc.… more
- Stanford University (Stanford, CA)
- CXR Senior Process and Integration Engineer **School of Engineering, Stanford, California, United States** Research Post Date Mar 10, 2025 Requisition # 105427 ... device fabrication, with strong knowledge of design, packaging, and test . Industry experience is a strong plus. The role...on research methods; educate and train users on research methodology and effective tools and techniques. + Supervise staff… more
- NVIDIA (Santa Clara, CA)
- …and play! For more details, see http://www.geforce.com/geforce-now . We are looking for a Senior Backend Software Engineer who sees the big picture of Cloud ... platform reliability. + Influence the technology stack, architecture, and development methodology . + Drive automation, monitoring, and performance tuning. + Build… more
- Amazon (Cupertino, CA)
- …monitoring tools and metrics to ensure hardware is running properly in both test and production environments. In addition, you will: - Partner with Hardware Design ... Engineers and Software Engineer undertake sustaining and root cause analysis of complex...design, tests and fleet deployment. - Help build robust methodology and processes to deliver technology to products About… more
- NVIDIA (Santa Clara, CA)
- …gaming, and AI. As part of the Silicon Solutions Team we seek a Senior Product Definition Engineer . Our team delivers groundbreaking solutions to productize ... time-to-market strategies. + Partner with the internal Tools and Methodology team to further improve the tools infrastructure and... team to further improve the tools infrastructure and test procedure. + Work alongside system architects, chip and… more
- Palo Alto Networks (Santa Clara, CA)
- …PDN networks; defining PCB routing constraints; reviewing PCB layout; developing test plans; performing hands-on measurements to validate critical interfaces. Within ... closely with Board Design, ASIC Design, PCB Layout, and Validation Test . You will also collaborate cross-functionally with Product Management, Platform Software,… more
- Google (Mountain View, CA)
- …languages such as UVM and SystemVerilog. + Experience developing and maintaining verification test benches, test cases, and test environments. Preferred ... enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM) or verify designs with SystemVerilog Assertions (SVA)… more
- Walmart (Sunnyvale, CA)
- …monitoring, performance, scalability, availability, security, and alerting for software test , integration, and production environments. + Plan and implement a ... availability bottlenecks for the application. + Develop, maintain, and enhance automated test cases and deployment procedures. + Follow coding and design best… more
- Qualcomm (Santa Clara, CA)
- …targets. You will work with engineers to develop and deliver the design and test it at unit-level and integrated-level test benches. Using these platforms, you ... You will make regular contributions to the overall improvement in design methodology to drive productivity and initiatives All Qualcomm employees are expected to… more
- Cisco (San Jose, CA)
- …for Cisco high-end switching products. * Development of simulation models, test plans, direct and random tests, code or functional coverage, multi-chip/system ... Verilog/UVM. * Experience with ASIC design and verification processes, debugging, methodology , and tools. * Experience in verifying blocks/clusters/full chip level… more