• DSP or Serdes RTL Sr Principal Digital…

    Cadence Design Systems, Inc. (San Jose, CA)
    …but is not limited to: + Digital microarchitecture definition and documentation + RTL logic design , debug and functional verification + Strong background in ... and developing flows at all phases of the digital design and functional verification. It is further expected that...the San Jose office. A Cadence satellite office (if senior with extensive SerDes exp.) will be considered. Position… more
    Cadence Design Systems, Inc. (10/17/25)
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  • Senior ASIC Design Engineer,…

    Amazon (Sunnyvale, CA)
    …Fire tablets, Fire TV and Amazon Echo. What will you help us create? The Role: As a Senior ASIC Design Engineer, you will be part of an advanced design and ... Communicate and work with team members across multiple disciplines * Develop detailed design specifications and documentation * Perform RTL coding and synthesis… more
    Amazon (12/12/25)
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  • Senior Applications Engineer - DDR…

    Cadence Design Systems, Inc. (San Jose, CA)
    …on memory subsystem verification and/or performance analysis* Strong knowledge of ASIC flow, RTL design in Verilog, System Verilog and FPGA design * ... to make an impact on the world of technology. Senior Applications Engineer - DDR Design IPJob...IPs and DDR protocols* Work closely with IP Sales staff , marketing and R&D teams to win opportunities* Run… more
    Cadence Design Systems, Inc. (01/10/26)
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  • FPGA Senior Design Engineer

    Cisco (Milpitas, CA)
    …features. **Your Impact** We are seeking a highly experienced and accomplished FPGA Senior Design Engineer to provide technical leadership and deep expertise in ... Take ownership of complex FPGA sub-modules, from micro-architecture definition to RTL implementation using Verilog/SystemVerilog or VHDL. + Design &… more
    Cisco (01/07/26)
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  • Sr Principal Hardware Security Engineer

    Oracle (Santa Clara, CA)
    … communities and audiences, consisting of varied roles and responsibilities (eg, architects, senior designers, junior design staff , technicians, etc.). + ... firmware. + FPGA implementation experience. Use of FPGAs in a hardware design context, and/or RTL /gateware implementation. \#LI-SM18 Disclaimer: **Certain US… more
    Oracle (11/25/25)
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  • Sr. Technical Program Manager, ASIC

    Amazon (Sunnyvale, CA)
    …through the various design phases of Silicon development from architecture definition, RTL design , Verification, IP design , Physical design , silicon ... of managing various phases of pre-silicon such as architecture, front end design , pre-silicon verification, FPGA prototyping, Emulation, Physical design , BROM,… more
    Amazon (11/27/25)
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  • ASIC Engineer, Leo Manufacturing

    Amazon (Sunnyvale, CA)
    …of our company DNA. As part of a project team you will work alongside Senior ASIC Engineers; supporting the design , debug, validation and optimization of the ... ASIC Engineer you will engage with an experienced cross-disciplinary staff to conceive and design innovative consumer...Engineering, Computer Engineering, or related fields - Experience in RTL coding and debug, as well as performance, power,… more
    Amazon (12/20/25)
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