• SanDisk (Milpitas, CA)
    …recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability ... of Memory teams to meet systems specs. + Define ASIC requirements for upcoming new NAND Flash based chips...requirements for upcoming new NAND Flash based chips and design systems algorithms. + Develop and maintain a System… more
    DirectEmployers Association (09/20/25)
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  • SanDisk (Milpitas, CA)
    …interface between various functional teams such as Test, Reliability, QA, Firmware, ASIC , NAND Design , Validation, Operations, and Manufacturing teams + ... recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability… more
    DirectEmployers Association (10/02/25)
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  • ASIC Engineer , Network

    Meta (Sunnyvale, CA)
    …and Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Network Design Verification Responsibilities: ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in … more
    Meta (09/30/25)
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  • Sr. SOC/ ASIC Physical Design

    SpaceX (Sunnyvale, CA)
    Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out ... this possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging… more
    SpaceX (09/11/25)
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  • ASIC Engineer , Design

    Meta (Sunnyvale, CA)
    …machine learning, video transcoding and network acceleration. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as… more
    Meta (08/01/25)
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  • ASIC /SOC DFT Engineer (Silicon…

    SpaceX (Sunnyvale, CA)
    …in scan insertion or DFT setup PREFERRED SKILLS AND EXPERIENCE: + Understanding of ASIC design flow, methodologies, physical design , and verification + ... ASIC /SOC DFT Engineer (Silicon Engineering) Sunnyvale,...will expand the performance and capabilities of the Starlink network . RESPONSIBILITIES: + Responsible for evaluating design more
    SpaceX (09/18/25)
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  • ASIC Engineer , Networking…

    Meta (Menlo Park, CA)
    **Summary:** As a Networking ASIC Engineer on the Infrastructure Silicon team at Meta, you will play a key role in shaping the networking architecture for ... and Program Management to deliver first-pass functional silicon. **Required Skills:** ASIC Engineer , Networking Architecture and Modeling Responsibilities: 1.… more
    Meta (10/20/25)
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  • ASIC /SOC DV Engineer (Silicon…

    SpaceX (Sunnyvale, CA)
    ASIC /SOC DV Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars is ... make this possible, with the ultimate goal of enabling human life on Mars. ASIC /SOC DV ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience… more
    SpaceX (09/19/25)
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  • Sr. SOC/ ASIC DFT Engineer (Silicon…

    SpaceX (Sunnyvale, CA)
    …hours and weekends as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer /Senior: $170,000.00 - $230,000.00/per year Your actual level and ... Sr. SOC/ ASIC DFT Engineer (Silicon Engineering) Sunnyvale,...will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design , validation, product engineering and ASIC implementation).… more
    SpaceX (09/09/25)
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  • ASIC Physical Design and Timing…

    NVIDIA (Santa Clara, CA)
    …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... and intelligence. What you'll be doing: + Drive Physical Design and timing analysis and closure of NVIDIA's GPUs,...experience in timing convergence for ASICs, CPUs, GPUs or Network processors. + Knowledge of deep sub-micron process nodes.… more
    NVIDIA (10/17/25)
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  • Senior ASIC Physical Design

    NVIDIA (Santa Clara, CA)
    …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... ECOs including crosstalk and noise analysis. + Expertise in physical design and optimization eg, placement, routing, cell sizing, buffering, logic restructuring,… more
    NVIDIA (08/23/25)
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  • Senior ASIC Front End Infrastructure…

    NVIDIA (Santa Clara, CA)
    NVIDIA is seeking elite ASIC RTL/Verification ASIC engineers to develop the core Verification and RTL infrastructure of the world's leading GPUs. This position ... team of dedicated Infrastructure engineers continuously upgrades the NVIDIA Hardware design environment. We focus relentlessly on Infrastructure improvement so that… more
    NVIDIA (10/28/25)
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  • Senior Signal Integrity Engineer (NetSec)

    Palo Alto Networks (Santa Clara, CA)
    …to validate critical interfaces. Within the Hardware team, you collaborate closely with Board Design , ASIC Design , PCB Layout, and Validation Test. You will ... Component Engineers. **Your Impact** + Collaborate with a cross-functional team including: ASIC , Board design , PCB layout, Operations supply base management,… more
    Palo Alto Networks (10/07/25)
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  • Senior Logic Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Logic Design Engineer with Physical Design background! As a member of our CPU Logic Design Team, you will be responsible for the ... design of CPU on-chip interconnect network and last-level caches , working closely with the...expertise is required as is a deep understanding of ASIC design flow including RTL design more
    NVIDIA (09/10/25)
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  • Senior System SW Engineer , System…

    Palo Alto Networks (Santa Clara, CA)
    …work on the development of ASICs, FPGAs and Systems that power Palo Alto Network 's Next Generation Firewall platforms **Your Impact** You will work on cutting edge ... for next generation firewall products, identify performance bottlenecks and solutions, design and model protocol and sub-component offload solutions. In addition to… more
    Palo Alto Networks (10/18/25)
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  • Staff Engineer , Networking

    Celestica (San Jose, CA)
    …Country: USA State/Province: California City: San Jose **Summary** We are seeking a **Staff Engineer , Networking** to join our Sonic NOS HDK Vertical team. This is a ... hands-on engineering position** focused on the **development and sustenance of Network Operating Systems (NOS)** for white-box switching platforms. The ideal… more
    Celestica (08/19/25)
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  • Senior Silicon Engineer

    Microsoft Corporation (Santa Clara, CA)
    …for passionate, high-energy engineers to help achieve that mission. As a Senior Silicon Engineer - ASIC verification in the Data Processing Unit team you will ... your career. We are looking for a **Senior Silicon Engineer ** to Join our team! **Responsibilities** + Lead key...+ Lead key components of functional validation of complex ASIC SOC using UVM/C test bench + Perform pre-silicon… more
    Microsoft Corporation (10/07/25)
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  • Signal Integrity Engineer

    Meta (Menlo Park, CA)
    …to leverage the efficiency gained by optimizing our AI, compute, storage and network platforms for our data centers. Our platform team is industry-leading in ... scalability, reliability, and intelligence. We are looking for a Signal Integrity Engineer to support the development of Meta's platforms and help shape the… more
    Meta (10/20/25)
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  • Electrical Engineer , Power

    Meta (Menlo Park, CA)
    …delivery validation and design 14. Experience with end-to-end power delivery network design , simulation (eg SIMPLIS, Sigrity PowerDC/SI, ANSYS SIWave or ... affecting billions of users. Meta is seeking an Electrical Engineer to join our Power Systems team. Our team...ASIC and/or FPGA, and related schematic and PCB design 10. Experience with analyzing and resolving power delivery… more
    Meta (10/22/25)
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  • Hardware Engineer , Platforms, University…

    Google (Sunnyvale, CA)
    …of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Hardware Engineer in the board and system design team, you will ... Hardware Engineer , Platforms, University Graduate _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Early** Experience completing work as directed, and… more
    Google (09/26/25)
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