- Qualcomm (San Diego, CA)
- …SoC Implementation Team is looking for skilled engineers to focus on timing constraints development, power analysis, STA , and timing closure for ... This is an excellent opportunity to join the Snapdragon implementation team, which is responsible for SoCs in sub-3nm...and low-power multi-voltage domain crossings, and signoff with static timing analysis. + Collaborate closely with RTL design… more
- Qualcomm (San Diego, CA)
- …+ Experience in static timing analysis, constraints and other physical implementation aspects + Familiar with digital flow design and industry standard ... tools used for RTL to GDS implementation + Good technical writing and communication skills in...debug across multi-mode, multi-voltage domain designs using industry standard timing tools + STA setup, convergence, reviews… more
- Qualcomm (San Diego, CA)
- …you will work with microarchitecture and RTL design team to develop timing constraints, drive implementation of the designs to meet aggressive power, area ... Design Timing Engineer,... automation using TCL/Perl/Python. + Familiar with digital flow design implementation RTL to GDS : ICC, Innovous… more
- Google (San Diego, CA)
- …silicon timing closure and chip integration. + Experience with STA signoff constraint authoring for full-chip level, tapeout signoff requirements, checklists, ... in state-of-the-art technology process nodes. + Experience with ASIC design flows and methodology of static timing ...full chip timing constraint creation and validation, timing signoff checklist criteria, perform full chip STA… more
- Qualcomm (San Diego, CA)
- …for all Qualcomm Business Units. Minimum Skill/Experience: + 2-10 yrs experience in Physical Design and timing signoff for high speed cores. + Should have good ... **Experience in leading block level or chip level Physical Design , STA and PDN activities** . +...Work independently in the areas of RTL to GDSII implementation . + Ability to collaborate and resolve issues wrt… more
- Qualcomm (San Diego, CA)
- …+ Work closely with verification/physical design team to complete the IP design implementation . + Support SoC team to integrate low power / power ... controller, on-chip sensor controller and digital power meter. + Perform RTL design , simulation, synthesis, timing analysis, lint check, clock domain crossing… more
- Qualcomm (San Diego, CA)
- …entire low power, high performance ASIC/SoC design flows (micro-architecture, RTL design , verification, synthesis, timing / STA , UPF, CLP, LEC formal ... using PowerArtist and PrimeTime PX (PTPX) and work with cross-functional teams - design , implementation , and physical design teams - to optimize power. +… more