- Acceler8 Talent (San Francisco, CA)
- Top-Level Design Verification Engineer - Datacenter AI Hardware Acceler8 Talent is partnering with a well‑funded startup (>$100m Series A), backed by ... world‑class investors, to hire an experienced Top-Level Design Verification Engineer . This team is building the next‑generation compute platform for… more
- SQL Pager LLC (San Francisco, CA)
- Principal /Senior Staff/Staff ASIC Design Engineer (RISC-V) Client Overview Client is building the first latency optimized SoC for their industry. Using its ... Job Responsibilities . We are seeking a dedicated CPU design engineer as part of ASIC for...Verilog/System Verilog, performance/speed/power goals. . Collaborate with Algorithm and Verification teams to design various functional IPs… more
- SQL Pager LLC (San Francisco, CA)
- Principal /Senior Staff/Staff GPGPU Design Engineer Client Overview Client is building the first latency optimized SoC for their industry. Using its proven AI ... industry by storm. Job Responsibilities . We are seeking a dedicated hands-on GPGPU Design Engineer to help develop an GPGPU for our artificial intelligence… more
- Vivid Technology (San Francisco, CA)
- Principal Analog & Mixed Signal IC Design Engineer Fresh off a successful funding round, this well-capitalized (Series B) start-up is pioneering a new ... system requirements and contribute to architecture discussions Own schematic design , pre-/post-layout simulation, and verification using industry-standard EDA… more
- City and County of San Francisco (San Francisco, CA)
- Senior Information Systems Engineer - Networks Specialty - City and County of San Francisco - Multiple Departments Citywide - 1043 Full-time Certification Rule: Rule ... List Work Hours: Regular Job Code and Title: 1043-IS Engineer -Senior Fill Type: Permanent Civil Service Eligible List Type:...the Journey level. This level is distinguished from the Principal level in that Senior level exercises no or… more
- Teleflex (Pleasanton, CA)
- Principal Engineer , Design Development, R&D **Date:** Dec 18, 2025 **Location:** Pleasanton, CA, US **Company:** Teleflex **Expected Travel** : Up to 10% ... Requirements** * Mastery of all phases of product development, including design verification , validation, implementation, and manufacturing. * Demonstrated… more
- City and County of San Francisco (San Francisco, CA)
- …the minimum qualifications. Application Deadline: Continuous How to Apply: Applications for Principal Information Systems Engineer - Networks Specialty are only ... that integrate these systems together as an enterprise networking backbone. The 1044 Principal Networks Engineer is the highest level in the Engineer… more
- City and County of San Francisco (San Francisco, CA)
- …minimum qualifications. Application Deadline: Continuous How to Apply: Applications for Principal Information Systems Engineer - Applications Specialty are only ... that integrate these systems together as an enterprise networking backbone. The 1044 Principal Applications Engineer is the highest level in the Engineer… more
- PagerDuty (San Francisco, CA)
- …and help build a more equitable world-all in a flexible, award-winning workplace. ** Principal Product Manager, Growth** PagerDuty is seeking a Principal Product ... optimization initiatives. You will collaborate closely with product, engineering, design , pricing, and go-to-market teams to transform PagerDuty's value realization… more
- Roche (Pleasanton, CA)
- …where every voice matters. **The Position** We are seeking a highly motivated Principal System Engineer I to join our End-to-End Solution Integration Chapter ... Python, JMP) to characterize, optimize, and set subsystem specifications. + Plan, design , and execute comprehensive Verification and Validation (V&V) test cases… more
