- Broadcom (San Jose, CA)
- …and develop scalable and reusable Testbench environment using the framework of Verification Methodologies. + Drive Test plans for all features for Block/Core/SOC and ... and get to full Functional coverage and bring the Verification to closure + Debug Regression failures, analyze Functional...in an efficient way. + Lead the documentation of verification strategy including Test plans, Verification Environment,… more
- Broadcom (San Jose, CA)
- …Architect and develop scalable and re-usable testbenches, using the framework of the verification methodology + Build pseudo-random tests to verify and get to full ... Coverage gaps and improve tests to cover the gaps + Document verification strategy including Test plans, Verification Environment, pseudo-random tests, etc.… more
- Insight Global (Milpitas, CA)
- …analog and mixed-signal semiconductor solutions is looking for a Senior or Principal IC Design Engineer to join their advanced connectivity team. This group ... a hands-on technical role requiring strong circuit-level design experience and full IC tapeout ownership. Key Responsibilities: Design and tapeout BiCMOS ICs for… more
- Broadcom (San Jose, CA)
- …checking, STA, RTL/gate level simulations & silicon debug Scripting for various IC design tasks such as STA, equivalency checks, test bench, simulations, synthesis, ... etc. prepare block level resource requirements & development schedule generate verification & test plans for design validation Perform design tradeoff analysis -… more
- Broadcom (San Jose, CA)
- …please Sign-In before you apply.** **Job Description:** Broadcom is searching for a Physical IC Design Engineer to join the Data Center Solutions Group. This ... the following:** + Execution of Physical Design, Synthesis, Physical Verification , and Timing Closure + Setup and Synthesizing RTL...Layout + Flow and Methodology Development + Collaborating with IC Design RTL Engineers + Must work in person… more
- Texas Instruments (Santa Clara, CA)
- …architecture and micro-architecture, RTL coding, simulation, synthesis, timing closure, verification , evaluation, debugging of high-speed SerDes chips both at the ... circuit level and behavioral level. As a design engineer , you will prepare test methods and specifications, assist...good understanding of analog functionality and exposure to analog IC design methods + Ability to solve problems using… more
- Broadcom (San Jose, CA)
- …Account, please Sign-In before you apply.** **Job Description:** ASIC/Layout Design Engineer : Oversees definition, design, verification , and documentation for ... pin assignment. + Perform blocks PnR, timing closure, physical verification . + Perform blocks IR/EM analysis. Experience with chip...make it more efficient. + Expertise on low power IC design is desirable. + Good knowledge on physical… more
- Broadcom (San Jose, CA)
- …Candidate Account, please Sign-In before you apply.** **Job Description:** **Job Description: IC Design Engineer ** + Participate in IP level architectural ... and Clock/Reset Domain crossing issues in the design + Collaborate with verification team on test plan development, debugging, and coverage closure + Collaborate… more
- Broadcom (San Jose, CA)
- …with custom routing for high speed interfaces, bump map design , routing and physical verification and tapeout to the foundries. As part of your job you will be ... (3DIC compiler), Mentor Graphics (Calibre) for layout generation, editing and verification + Strong understanding of TSV design, micro-bumps, solder bumps, and… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …who want to make an impact on the world of technology. Senior Principal Design Engineer The Sr Principal Analog IC Designer is responsible for design and ... developing analog/mixed-signal IC circuit blocks, the architecture and initial concept/specification through final verification of conformance to customer… more
- Broadcom (San Jose, CA)
- …compute cores and CPUs. We are seeking a motivated and technically strong engineer to join our team. Job Description: Layout design of digital high-performance ... the blocks with best PPA (power/performance/area) Debug LVS/DRC/ERC errors with verification tool Analyze the trade-offs and performance implications of different… more
- Broadcom (San Jose, CA)
- …AI compute cores and CPUs. We are seeking a motivated and technically strong engineer to join our team. Layout design of digital high-performance blocks + Timing ... blocks with best PPA (power/performance/area) + Debug LVS/DRC/ERC errors with verification tool + Analyze the trade-offs and performance implications of different… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …technical skills to enable semiconductors companies adopting Cadence solutions and associated IC design methodologies. The Application Engineer will work with ... automation). Job Responsibilities: + Acquire strong technical understanding of the complete IC design/ verification flow with focus on analog design automation +… more
- Power Integrations (San Jose, CA)
- Job Description: The Senior Failure Analysis Engineer will perform power supply or system level failure analysis to support RMA and internal/external customer ... include, but are not limited to, the following. + Debugging and functionality verification of AC/DC switching power supply modules in various topologies using Power… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …the world of technology. Job Description for R&D Solutions Role: The Physical Verification Solutions Engineer role focuses on validating and optimizing advanced ... Fill, and PERC (Parameterized Electrical Rule Check)-to enable next-generation verification methodologies for high-performance IC development. Desired Skills… more
- Google (Sunnyvale, CA)
- Staff Quality and Reliability Engineer , Google Cloud _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Advanced** Experience owning outcomes and decision making, ... in semiconductor reliability and manufacturing processes (fab, assembly, test), or IC and packaging failure mechanisms and related failure analysis. + Knowledge… more
- NVIDIA (Santa Clara, CA)
- …to do their best work. ATE/SLT hardware team provides the interface hardware of IC package testing at final test and system level test. Hardware includes highly ... for both product bring-up and HVM, design and manufacture improvement, and verification /debug, to production support. What you'll be doing: + Review and approve… more
- Meta (Sunnyvale, CA)
- …the future of Wearables and Mixed Reality (MR) products. As a Display Electrical Engineer , you will be a member of our Reality Labs AR display engineering ... organization, involved with display module electrical design along with validation and verification , be the point of contact and interface to the product development… more
- NVIDIA (Santa Clara, CA)
- …and maintaining CAD tools used by IC designers including Virtuoso, IC -Manage, DRC/LVS verification tools, extractions, and spice simulation tools. + Work ... NVIDIA is searching for a motivated CAD Engineer to join the Advanced Technology Group. You...are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …to make an impact on the world of technology. Job Title: Lead Application Engineer Location: Tampere, Finland Reports to: AE Director Job Overview: This Digital ... IC design and support role offers an opportunity to...Logical Equivalency Checking + Low Power Design Implementation, SDC Verification + Place and Route + Parasitic Extraction, Timing… more