• Ethernovia (San Jose, CA)
    …their design from concept to silicon to their next car. Senior ASIC Front-End Design Engineer Summary: As a Senior ASIC Front-End Design Engineer , you will be ... for all aspects of digital SoC design , from micro-architecture specification, RTL, verification , synthesis, lint, CDC, LEC, and static timing analysis to deliver a… more
    job goal (01/14/26)
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  • Persimmons, Inc. (San Jose, CA)
    …we want to talk to you. What You'll Do As a Senior ASIC Design Engineer , you will be responsible for building and verifying the Persimmons Chiplet that will run ... open source IP Partner with DV engineers to develop comprehensive verification strategies, drive coverage closure, and debug complex cross‑functional issues Develop… more
    job goal (01/14/26)
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  • Persimmons Inc. (San Jose, CA)
    …want to talk to you. What you'll do: As a Persimmons Senior ASIC Design Engineer , you will be responsible for building and verifying the Persimmons Chiplet that will ... open source IP. Partner with DV engineers to develop comprehensive verification strategies, drive coverage closure, and debug complex cross-functional issues.… more
    job goal (01/14/26)
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  • Cognichip (Redwood City, CA)
    …nexus of silicon design and machine learning. As a Staff Chip Design Engineer on our team, you'll tackle real-world scientific and coding challenges-defining the ... of experience in RTL design, or a combination of design and verification Proficiency in SystemVerilog and Python languages Excellent written and verbal communication… more
    job goal (01/14/26)
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  • Senior Electrical PCIe Engineer

    Micron Technology, Inc. (San Jose, CA)
    …innovative solutions that drive the future of technology! **Position Overview:** As a Senior Electrical PCIe Engineer at Micron in San Jose, CA, you will play a ... or related field. + Minimum 5 years of experience in design, verification , and analysis of PCIe subsystems. + Expertise in PCIe protocols and architecture… more
    Micron Technology, Inc. (11/14/25)
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  • Senior PCIe Post-Silicon Validation…

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior Post-Silicon Validation Engineer to join our team! NVIDIA has continuously reinvented itself over the past two decades. Our invention ... and implementation, define the validation scope, develop the post-silicon verification infrastructure (Testplans, Tests, Scripts to analyze data), implement… more
    NVIDIA (01/10/26)
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  • Senior ASIC Verification Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Verification Engineer ! NVIDIA is seeking an outstanding engineer to verify the design and implementation of the world's ... collaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks. What you'll be...will be creating models, verifying functionality and performance of PCIe and CXL designs + Understand the design, define… more
    NVIDIA (10/18/25)
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  • Senior System Verification Engineer

    NVIDIA (Santa Clara, CA)
    …and intelligence. Join us today! We are now looking for a Senior System Verification Engineer to join our Emulation division and will be working onsite ... environment issues. + Bring-up and verify High Speed protocols like PCIe /CXL/NVLINK/IB/Ethernet etc Low speed protocols like I2C/I3C/SPI/UART + Bring-up/debug issues… more
    NVIDIA (01/10/26)
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  • ASIC Engineer , SoC Verification

    Meta (Sunnyvale, CA)
    **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... Chip (SoC) for data center applications. As a Design Verification Engineer , you will be part of...- Chip Debug, Boot, CPU Subsystems, Chip level Clock/Reset, PCIe , NIC, Memory Subsystems 18. Familiarity with developing System… more
    Meta (12/20/25)
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  • ASIC Engineer , Design Verification

    Meta (Sunnyvale, CA)
    **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... On Chip (SoC) for data center applications.As a Design Verification Engineer , you will be part of...verification cycle 16. Experience with IP or integration verification of high-speed interfaces like PCIe , RoCE,… more
    Meta (12/20/25)
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  • ASIC Engineer , Design Verification

    Meta (Sunnyvale, CA)
    **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... On Chip (SoC) for data center applications.As a Design Verification Engineer , you will be part of... of high-speed interfaces like Peripheral Component Interconnect Express ( PCIe ), Double Data Rate (DDR), Ethernet 16. Experience with… more
    Meta (12/20/25)
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  • Senior ASIC Verification Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Verification Engineer for our Coherent High Speed Interconnect team! For two decades, we have pioneered visual computing, ... most sophisticated problems in everyday life. As a ASIC Verification Engineer at NVIDIA, you will verify...interconnects. + Knowledge of industry standard interconnect protocols like PCIE , CXL, CHI will be useful. + Strong background… more
    NVIDIA (01/10/26)
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  • HBM/DDR/SerDes DFT Verification Lead…

    Broadcom (San Jose, CA)
    …Jose, California Development Center. We are seeking a highly skilled HBM and SerDes DFT Verification Engineer to join our dynamic team. In this role, you will ... Broadcom's ASIC Product Division is seeking candidates for HBM/DDR/SERDES Verification Lead Engineer position at our San...MBIST, IEEE1687 and others) + Proven experience in DFT verification , particularly with HBM, DDR, PCIE and… more
    Broadcom (12/06/25)
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  • Senior Verification Engineer

    Microsoft Corporation (Mountain View, CA)
    …will manage and optimize the Cloud infrastructure. We are looking for a **Senior Verification Engineer ** to join the team. **Responsibilities** The role will be ... responsible for pre-silicon functional verification , creation of verification environments and tests...utilizing AI in the day-to-day work + Experience with PCIe subsystems + Experience with the use of formal… more
    Microsoft Corporation (12/17/25)
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  • IC Verification Engineer

    Broadcom (San Jose, CA)
    …and develop scalable and reusable Testbench environment using the framework of Verification Methodologies. + Drive Test plans for all features for Block/Core/SOC and ... and get to full Functional coverage and bring the Verification to closure + Debug Regression failures, analyze Functional...engineers **These requirements are a plus:** + Experience in PCIe protocol + Scripting knowledge of Python or Perl… more
    Broadcom (12/18/25)
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  • IC Verification Engineer

    Broadcom (San Jose, CA)
    …Architect and develop scalable and re-usable testbenches, using the framework of the verification methodology + Build pseudo-random tests to verify and get to full ... and improve tests to cover the gaps + Document verification strategy including Test plans, Verification Environment,...+ A good understanding of a complex protocol like PCIe or other multi-layered protocol will be a plus… more
    Broadcom (12/30/25)
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  • Sr SOC Verification Engineer

    Amazon (Cupertino, CA)
    …and Japan, and customers across all industries. We are seeking experienced Design Verification Engineers to build the next generation of our cloud server chips. Our ... or CS or CE. - 8+ years of design verification experience using System Verilog and UVM - 8+...eg AHB/APB/AXI - Experience with interconnect protocols, for eg PCIe and UCIe - Experience with memory sub-systems, including… more
    Amazon (12/04/25)
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  • Staff Logic Design Engineer

    Teledyne (Milpitas, CA)
    …networking. **Role Overview** We are looking for a top-notch Staff Logic Design engineer who has the right composition of knowledge, experience, team play, spirit ... products. Join our high-speed Protocol Team as a **Staff** **Logic Design Engineer ** , where you'll architect and implement high-performance digital logic for… more
    Teledyne (11/18/25)
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  • Lead HW Post-Silicon Validation Engineer

    Cisco (San Jose, CA)
    …company in the world. You will engage in dynamic collaboration with verification engineers, designers, and cross-functional teams, working together to ensure the ... successful verification of the ASIC throughout its lifecycle. Operating at...Impact:** We are seeking a Senior HW Post-Silicon Validation Engineer with deep expertise in lab-intensive **hardware** validation to… more
    Cisco (01/07/26)
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  • Hardware Engineer

    Cisco (Milpitas, CA)
    …**Your Impact** We are looking for a skilled and proactive FPGA Design Engineer with 3+ years of industry experience to manage and implement complex digital ... in the full FPGA development lifecycle, including independent RTL coding, verification , high-speed design practices, and debugging on hardware. The Intermediate … more
    Cisco (12/16/25)
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