- NVIDIA (Santa Clara, CA)
- …team and see how you can make a lasting impact on the world. We seek an RTL Analysis Methodology Engineer to join our Logic Design Implementation team. ... verification methodologies. + Contribute to architecting and developing brand-new RTL analysis flows. + Serve as an...documents and train internal users. + Use data collection, analysis , and reporting tools to provide methodology … more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Power Optimization and Analysis Engineer ! NVIDIA prides ourselves in having energy efficient products. We believe that continuing ... NVIDIA GPUs. As a member of the Power Modeling, Methodology and Analysis Team, you will collaborate...internally developed tools and industry standard pre-silicon gate-level and RTL power analysis tools, to help improve… more
- Microsoft Corporation (Mountain View, CA)
- …will: + Establish Logical Equivalence Checking (LEC)/Formal Equivalence Verification (FEV) methodology for hierarchical and block-level partitions between RTL , ... and have a keen interest in driving the associated methodology for large and intricate digital System on Chip...CAD (Computer Aided Design) flow systems + Perform detailed debug/ analysis to guide the RTL and physical… more
- SpaceX (Sunnyvale, CA)
- …for test modes + Timing closure ownership throughout the entire project cycle ( RTL , synthesis, and physical implementation) + Analysis of clock domain crossing ... SOC/ASIC Synthesis & Front-End STA Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX...teams to drive integration, timing, logical equivalence checking and analysis of various IPs into RTL +… more
- Microsoft Corporation (Santa Clara, CA)
- …Design) , Design Verification, Validation, Design for testing (DFT), Emulation, Design Synthesis, RTL Power Analysis , Physical Design ( PD) Handoff and System on ... Solutions Team is looking to hire a **Senior Silicon Engineer ** to join our Central Front-End Tools, Flows and...** to join our Central Front-End Tools, Flows and Methodology (TFM **)** group. This team drives state-of-the-art converged… more
- Qualcomm (Santa Clara, CA)
- …help create a smarter, connected future for all. As a Qualcomm GPU Engineer , you may architect, design, implement, verify, and/or optimize the performance and power ... Engineering, or related work experience. **Job Description:** + Synthesize the Verilog RTL and create models and compile them to emulators like Veloce/Palladium/Zebu… more
- Actalent (Sunnyvale, CA)
- …Netlist for Timing Area Power. Debug the timing/area/congestion issues and work with RTL Physical designers to resolve them. Qualifications: + 10 Years of experience ... in backend implementation such as synthesis timing closure power analysis etc. + Experience with power analysis ...and tools like PTPX must have. + Experience with RTL Synthesis and design optimization for Power Performance Area.… more
- Siemens Digital Industries Software (Fremont, CA)
- …responsible for technical selling and support of PowerPro, a leading-edge platform for RTL /gate Power analysis and optimization. This includes, but is not ... required. Job Qualifications *5+ years of industry experience as an Applications Engineer or related field. *Proven hands-on ASIC RTL VHDL/Verilog/SystemVerilog… more
- ManpowerGroup (San Jose, CA)
- …need:** + A minimum of 3 years of experience with STA (Static Timing Analysis ) and PrimeTime and related timing constraints methodology and SDC constraints ... time to market. **You Are:** An experienced SoC Integration Engineer **The Work:** The ideal candidate can help along...language + A minimum of 3 years of experience RTL Integration, 3 rd Party IP RTL … more
- NVIDIA (Santa Clara, CA)
- …are now looking for a motivated Senior ASIC Physical Design PPA (Performance, Power, Area) Engineer to join our dynamic and growing team. If you are looking for a ... NVIDIA's designs + Apply knowledge and gain experience in ASIC design including RTL and logic design, physical and circuits design, and timing and power convergence… more
- Qualcomm (Santa Clara, CA)
- …**General Summary:** As a CAD Engineer focusing on the post silicon methodology and support, you will work with RTL , architecture, design, DV, software, ... low level HW/SW interaction and debug + Experience with RTL & Gate Level Simulations + Experience with power... & Gate Level Simulations + Experience with power analysis methodology **Principal Duties and Responsibilities:** *… more
- NVIDIA (Santa Clara, CA)
- …is our life's work, to amplify human inventiveness and intelligence. Are you a software engineer with a passion for hardware, ASIC design and VLSI? Be part of a ... diverse team crafting NVIDIA's chip design methodology ! We're responsible for NVIDIA's front-end ASIC...! We're responsible for NVIDIA's front-end ASIC software including RTL synthesis, equivalence checking, and early physical design and… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Physical Design and Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part of ... + Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing...experience to improve the convergence flows working with the Methodology Team. What we need to see: + BS… more
- Microsoft Corporation (Santa Clara, CA)
- …experience to customers and partners worldwide and we are looking for passionate engineer to help achieve that mission. Are you seeking an opportunity to work ... within the Azure Hardware Systems & Infrastructure group is seeking a Senior Silicon Engineer - IO. You will join our front-end silicon team and be responsible for… more
- Siemens Digital Industries Software (Fremont, CA)
- …+ Working knowledge of IC EDA tools and design methods including: o ASIC design methodology from RTL Synthesis to Physical Implementation phases o RTL ... planning, physical design/verification, muti-die based electrical, thermal, mechanical stress analysis and manufacturing test of advanced 2.5 and 3D… more
- Siemens Digital Industries Software (Fremont, CA)
- …+ Detailed knowledge of IC EDA tools and design methods including: o ASIC design methodology from RTL Synthesis to Physical Implementation phases o RTL ... planning, physical design/verification, muti-die based electrical, thermal, mechanical stress analysis and manufacturing test of advanced 2.5 and 3D… more
- NVIDIA (Santa Clara, CA)
- …reduce power consumption of NVIDIA GPUs. As a member of the Power Modeling, Methodology and Analysis Team, you will collaborate with Architects, ASIC Design ... We are now looking for an Architecture Energy Modeling Engineer ! At NVIDIA, we pride ourselves in having energy-efficient products. We believe that continuing to… more
- NVIDIA (Santa Clara, CA)
- …verification methodology + Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis + Excellent ... for System-level modules (Fuse, Strap, Floorsweep, In-silicon measurement, Reset, Sysctrl) + RTL design, synthesis, timing + Silicon bring-up + SOC level integration… more
- Amazon (Sunnyvale, CA)
- …that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers. We are a part of ... patterns generation, chip bring-up and more. As a DFT Engineer , you will impact and see the device through...- Review sign-off level timing closure using static timing analysis of various DFT modes - Contribute to wafer… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior ASIC Engineer , Timing to join our dynamic and growing team. If you are looking for a challenging and exciting role in ... asynchronous checking including clock domain crossing checks and MTBF analysis , logic synthesis, netlist quality checks, etc. + Help...teams. + Work on project execution as well as methodology improvements. What we need to see: + BS… more