- SpaceX (Sunnyvale, CA)
- Sr . Full Chip Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out ... the ultimate goal of enabling human life on Mars. SR . FULL CHIP PHYSICAL...and weekends as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer/ Senior : $170,000.00 - $230,000.00/per year… more
- Amazon (Cupertino, CA)
- …and model power consumption with high accuracy. Key job responsibilities - Responsible for full chip power analysis & modelling at various stages of design (RTL ... used to power today's AI workloads in datacenters all around the world. As a Sr . SoC Power Engineer, you'll contribute to the project at the ground level by modeling… more
- Amazon (Cupertino, CA)
- …US, Europe, Singapore, and Japan, and customers across all industries. Custom SoCs (System on Chip ) live at the heart of AWS Machine Learning servers. As a member of ... and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and… more
- Amazon (Cupertino, CA)
- …US, Europe, Singapore, and Japan, and customers across all industries. Custom SoCs (System on Chip ) live at the heart of AWS Machine Learning servers. As a member of ... integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze new technologies...of a total compensation package, in addition to a full range of medical, financial, and/or other benefits. For… more
- NVIDIA (Santa Clara, CA)
- …of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as ... and intelligence. We are now looking for a motivated Senior ASIC Physical Design Engineer, Netlisting to...+ Background with logic synthesis at either block or full - chip level, at project execution and/or flow… more
- NVIDIA (Santa Clara, CA)
- …of Nvidia's GPUs, CPUs, DPUs and SoCs at block level, cluster level, and/or full chip level. + Help in driving frontend and backend implementation including ... with 2+ years experience in Synthesis and Timing + Hands-on experience in full - chip /sub- chip Static Timing Analysis (STA), timing constraints generation and… more
- Google (Sunnyvale, CA)
- Senior ASIC Physical Design Engineer _corporate_fare_...+ Contribute to the design and closure of the full chip and individual blocks from RTL-to-GDS. ... equivalent practical experience. + 7 years of experience with physical design (eg from RTL to GDSII, including key...collaborate with RTL, Design for Testing (DFT), Floorplan, and full - chip Signoff teams. Additionally, you'll solve technical… more
- Cisco (San Jose, CA)
- …ASIC experience. + Experience with microarchitecture and RTL implementation. + Experience with block/ full chip SDC development in functional and test modes. + ... ** Sr . ASIC Engineer** The application window is expected...will collaborate with Front-end and Back-end teams to understand chip architecture and guide them in refining design and… more
- Applied Materials (Santa Clara, CA)
- …wherever you may go. Learn more about our benefits (https://hrportal.ehr.com/applied/) . Physical Security Technologist Senior Manager leads the global strategy, ... global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service… more
- Applied Materials (Santa Clara, CA)
- …global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service ... is the leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. Our expertise in modifying materials at… more
- Google (Sunnyvale, CA)
- Senior Systems Engineer, Platforms _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving problems, and mentoring more ... _info_outline_ X This is a specialized role which requires physical interaction with hardware equipment in a simulated data...and contributing to research and project planning. From the chip to the data center, you are responsible for… more
- Celestica (San Jose, CA)
- …to manufacturing. + Conduct thermal simulations, postprocessing, and analysis ranging from chip to facilities level to verify thermal feasibility, risk, and to ... heat transfer hardware. + Consider the thermal aspects of chip packaging technologies. + Apply best-in-class fluid flow geometry...when possible and liquid cooling when necessary to achieve full performance and reliability at the lowest cost. +… more
- Celestica (San Jose, CA)
- …09 **IC/MGR:** Individual Contributor **Direct/Indirect Indicator:** Indirect **Summary** The Senior Lead Software Engineer designs, develops, and maintains software ... and capable of mentoring a team of engineers. The Senior Lead Engineer, Software will work in cross functional...knowledge of BMC related Hardware such as ARM, BMC chip (AST 2500, AST2600, Pilot 4 etc.), HW-monitor and… more
- Google (Fremont, CA)
- Senior Silicon Bringup and Test Lead, Raxium _corporate_fare_ Google _place_ Fremont, CA, USA **Advanced** Experience owning outcomes and decision making, solving ... qualifications:** + 15 years of experience in Application-Specific Integrated Circuit/System on Chip (ASIC/SoC) design, with a focus on both digital logic design and… more
- Microsoft Corporation (Mountain View, CA)
- …will manage and optimize the Cloud infrastructure. We are looking for a ** Senior Verification Engineer** to join the team. **Responsibilities** The role will be ... leading pre-silicon verification of blocks and sub systems through full cycle + 2+ years of experience in mentoring...developing tests, and debugging designs + Solid understanding of chip and/or computer architecture + Experience writing tests in… more
- Cisco (San Jose, CA)
- …CMOS products. * You will lead efforts for a large block on a complex chip , mentor team members and track deliverables, participate in peer review of complex IC ... solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security,… more
- Google (Sunnyvale, CA)
- …is a part of everything we do. The Data Center Engineering team takes the physical design of our data centers into the future. Our lab mirrors a research and ... make a huge impact. You generate ideas, communicate recommendations to senior -level executives and drive implementation alongside facilities technicians. With your… more
- Micron Technology, Inc. (San Jose, CA)
- …performance and reliability of non-volatile memory products. **Position Overview** The Senior Member of Technical Staff Design Engineer in Micron's NVEG organization ... and optimization of datapath circuits for NAND flash memory. This senior -level position will support design feasibility studies, evaluate impacts, and explore… more
- Cisco (San Jose, CA)
- …pioneer next-generation Silicon Photonics technologies. You will also engage directly with senior technical leaders and management across Cisco Fabs and the OSAT ... control) and data analysis skills. + Knowledge and experience in physical failure analysis **Preferred Qualifications** + Experience in Silicon Photonic packaging… more
- Cisco (San Jose, CA)
- …lead in San Jose, CA. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive high-quality DFT ... solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security,… more