- Google (Mountain View, CA)
- …technology process nodes. + Experience with ASIC design flows and methodology of static timing analysis . + Experience in extraction of design ... Google (https://careers.google.com/benefits/) . + Be responsible for delivering System-on-Chip (SoC) Static Timing Analysis . + Define SoC timing signoff… more
- Google (Sunnyvale, CA)
- … (ie, full chip timing signoff ownership, constraint authoring and verification, full chip static timing analysis and timing ECO creation, timing ... crosstalk. Preferred qualifications: + 10 years of experience in the domain of static timing analysis . + Experience leading one or more aspects of physical… more
- Google (Sunnyvale, CA)
- … (eg, full chip timing signoff ownership, constraint authoring and verification, full chip static timing analysis and timing ECO creation, timing ... crosstalk). Preferred qualifications: + 7 years of experience in the domain of static timing analysis . + Experience leading one or more aspects of physical… more
- Meta (Sunnyvale, CA)
- …Engineers within our Infrastructure organization. **Required Skills:** ASIC Implementation Engineer - Static Verification Responsibilities: 1. Perform Flat ... work with the Designers to create waivers 4. Perform RTL Design for Testability Analysis and improve the Design for Testability coverage for Stuck-at faults 5. Run… more
- NVIDIA (Santa Clara, CA)
- …with 2 years experience in Timing and STA + Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing ... intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and...inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs,… more
- NVIDIA (Santa Clara, CA)
- …+ 8+ years experience in Physical design/ Timing . + Experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and ... CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and...+ You will be responsible for all aspects of timing including, timing analysis and… more
- Cisco (San Jose, CA)
- ASIC Design Engineer - Design & Timing Constraints...development in functional and test modes + Experience in Static Timing Analysis and prior ... of our systems, leveraging the latest technology. We're seeking a talented ASIC engineer with a proven track record in high-performance products, ready to make a… more
- NVIDIA (Santa Clara, CA)
- …Engineering or related field (or equivalent experience). + 6+ years of experience in static timing analysis , methodology, or constraint development. + Strong ... work, to amplify human inventiveness and intelligence. We are seeking a highly skilled Timing Methodology Engineer with expertise in asynchronous timing and… more
- NVIDIA (Santa Clara, CA)
- …next generation of high-performance IPs for CPU, GPU and SOC designs. + Owning static timing analysis and convergence of high-performance designs. + You ... be responsible for all aspects of timing including setting up timing constraints, timing analysis and closure, ECO implementation, and timing … more
- Qualcomm (Santa Clara, CA)
- …setup for various modes/corners and low-power multi-voltage domain crossings, and signoff with static timing analysis . + Collaborate closely with RTL design ... Team is looking for skilled engineers to focus on timing constraints development, power analysis , STA, and timing closure for premium-tier chips.… more
- Cisco (San Jose, CA)
- …with block/full chip SDC development in functional and test modes. + Experience in Static Timing Analysis and prior working experience with STA tools ... ASIC Design Technical Leader - Design & Timing Constraints Focus Apply (https://jobs.cisco.com/jobs/Login?projectId=1432242) + Location:San Jose, California, US +… more
- Meta (Sunnyvale, CA)
- …designs, including physical-aware logic synthesis, floorplan, place and route, clock tree synthesis, static timing analysis , IR drop, EM, and physical ... and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical...H-Tree, and clock power reduction techniques 21. Knowledge of static timing analysis and concepts,… more
- Meta (Sunnyvale, CA)
- …field, or equivalent practical experience 10. 12+ years of experience in: STA ( Static Timing Analysis ), Modeling, Signoff methodology development and flows, ... **Summary:** Meta is hiring Application-Specific Integrated Circuit Engineer (ASIC) Methodology Engineer our Infrastructure organization, where you'll play a… more
- Meta (Sunnyvale, CA)
- …low-power ML Hardware design including physical-aware logic synthesis, floorplan, place and route, static timing analysis , IR Drop, EM, and physical ... area) of the design. **Required Skills:** Silicon Physical Design Engineer Responsibilities: 1. Develop and own physical design implementation...synthesis QoR on low power designs 14. Knowledge of static timing analysis and concepts,… more
- SpaceX (Sunnyvale, CA)
- …solutions and drive execution + Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, ... SOC/ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the… more
- Arrow Electronics (San Jose, CA)
- …with **block/full chip SDC development** in functional and test modes. + Experience in ** Static Timing Analysis ** and prior working experience with STA tools ... **Position:** SDC Engineer (eInfochips Inc) **Job Description:** **Position: SDC ...with physical design and DFT teams to close **fullchip timing ** in multiple timing modes. + Option… more
- NVIDIA (Santa Clara, CA)
- …EE background with an in-depth understanding of circuits, simulation, library characterization and static timing analysis ? Enjoy working on the cutting edge ... We are now hiring for a Senior Library Design Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the… more
- Meta (Sunnyvale, CA)
- …plan development and verification. 3. Define timing constraints, run synthesis and static timing analysis . 4. Support the test program development, chip ... **Summary:** As a Digital Design Engineer at Meta Reality Labs, you will work...blocks into larger SOC environments. 7. Assist with performance/power analysis of the design and help meet the power… more
- Cisco (San Jose, CA)
- …working with Verilog or System Verilog programming skills + Experience with simulators/synthesis/ static timing constraints and related tools (eg, VCS, DC, ... , performance, and power requirements. + Contribute to full chip integration and timing methodology/ analysis . + Develop and analyze functional coverage. + Help… more
- NVIDIA (Santa Clara, CA)
- …ADC etc. + Hands on experience running Spice simulations, EM/IR analysis , and static timing analysis /closure + Experience with spice simulation for noise ... are now looking for a motivated Senior Circuit Design Engineer to join our dynamic and growing team. If...challenging and exciting role in improving the netlist and timing quality of our designs and if you are… more