- Efficient Computer (San Francisco, CA)
- If you are an ASIC Physical Design Engineer who wants to impact the transformation of the next evolution of computing, we would like to talk to you. ... Efficient is hiring a senior ASIC Physical Design Engineer with experience in backend implementation from Netlist to GDSII. We seek individuals to… more
- Blue Origin (San Francisco, CA)
- …Engineering, Computer Engineering, or related technical discipline Experience with FPGA and/or ASIC design Proficiency in HDL programming (VHDL, Verilog, and/or ... Strong object‑oriented programming and scripting skills (Python, TCL, Perl) Experience with physical design flows and industry‑standard EDA tools Experience with… more
- SQL Pager LLC (San Francisco, CA)
- Principal/Senior Staff/Staff ASIC Design Engineer (RISC-V) Client Overview Client is building the first latency optimized SoC for their industry. Using its ... Job Responsibilities . We are seeking a dedicated CPU design engineer as part of ASIC...SoC level integration and verifications. . Work with the Physical design team for the timing closure… more
- OpenAI (San Francisco, CA)
- Join to apply for the Physical Design Engineer role at OpenAI About The Team OpenAI's Hardware team designs the custom silicon that powers the world's most ... Silicon Implementation Engineer with deep expertise in physical design and methodology. This individual contributor...area trade‑offs, working in collaboration with EDA vendors and ASIC partners Qualifications BS w/ 4+ or MS with… more
- OpenAI (San Francisco, CA)
- …a highly skilled Silicon Implementation Engineer with deep expertise in physical design and methodology. This individual contributor role sits within our ... physical design team and is central to... physical design team and is central to delivering power, performance,...area trade‑offs, working in collaboration with EDA vendors and ASIC partners Qualifications: BS w/ 4+ or MS with… more
- SQL Pager LLC (San Francisco, CA)
- Principal/Senior Staff/Staff GPGPU Design Engineer Client Overview Client is building the first latency optimized SoC for their industry. Using its proven AI ... Responsibilities . We are seeking a dedicated hands-on GPGPU Design Engineer to help develop an GPGPU...SoC level integration and verifications. . Work with the Physical design team for the timing closure… more
- Career Mentors, LLC (San Francisco, CA)
- …rigor, and realism Seniority & Experience 4-10 years of experience as a Hardware Design Engineer with front-end ASIC /SoC RTL focus Proven experience in ... Founding Hardware Design Engineer (Path to Director of...constraint-heavy domains , enabling AI models to reason about, design , and validate physical systems. Starting with… more
- Renesas Electronics Corporation (San Francisco, CA)
- …static timing analysis, logic equivalent checking to post-layout checking. Experience in DFT or physical design is a plus. Experience in FPGA prototype and lab ... Application/GUI team in FPGA prototype and lab debugging. Perform physical silicon device evaluation where necessary. Qualifications 10+ years...a plus. Fluent in either Verilog RTL coding and ASIC design methodology. Competence in developing … more
- Persimmons, Inc. (San Jose, CA)
- …making a global impact, we want to talk to you. What You'll Do As a Senior ASIC Design Engineer , you will be responsible for building and verifying the ... that balance performance, power, area & schedule Collaborate with physical design teams to ensure RTL quality...Computer Engineering, or related field 5+ years of hands‑on ASIC design experience with complex digital logic… more
- Persimmons Inc. (San Jose, CA)
- …global impact - we want to talk to you. What you'll do: As a Persimmons Senior ASIC Design Engineer , you will be responsible for building and verifying the ... that balance performance, power, area & schedule. Collaborate with Physical Design teams to ensure RTL quality...Computer Engineering, or related field 5+ years of hands‑on ASIC design experience with complex digital logic… more
- Grafton Sciences (San Francisco, CA)
- …at Grafton Sciences. About Grafton Sciences We're building AI systems with general physical ability - the capacity to experiment, engineer , or manufacture ... Senior Toolchain Engineer , Firmware Join to apply for the Senior...reproducible. This role is ideal for someone who can design production‑grade RTL and verification, understands FPGA/ ASIC … more
- Cisco Systems (San Francisco, CA)
- …and sustain strong relationships with cross-functional teams while collaborating on ASIC Design and Verification for reliable, high-performance products. Drive ... Open-minded, driven, diverse and deeply creative people at Cisco design the hardware that makes the internet work. Bring...power how humans and technology work together across the physical and digital worlds. These solutions provide customers with… more
- Microchip (San Jose, CA)
- …partnership with different teams within the FPGA business unit spanning architecture, ASIC design , verification, physical implementation, and test ... Senior Technical Staff Engineer - Design for Test Company...implement the testability features into the combined FPGA and ASIC SOC. The DFT lead will be involved from… more
- Advanced Micro Devices, Inc. (San Jose, CA)
- …a team where communication and teamwork are highly valued. Key Responsibilities As an ASIC Design Engineer , your responsibilities span various aspects of SOC ... members of the SOC Design - Verification, Emulation, STA, and Physical Design teams Support all front end integration activities (Lint, CDC, Synthesis, and… more
- MediaTek (San Jose, CA)
- …Architect Sunnyvale, CA $170,000.00-$240,000.00 2 weeks ago Senior Software Engineer , ASIC Verification Tools Mountain View, CA $174,000.00-$258,000.00 ... group of system architects, packaging technology developers, and SoC design experts dedicated to creating high-performance, efficient, and reliable solutions.… more
- Cisco (San Jose, CA)
- …that working in a smaller ASIC team can provide. **Your Impact** As an ASIC Design Verification Engineer , you will play a critical role in developing ... (eg, Jasper or VC Formal) + Experience with RTL Design desirable + Familiarity with ASIC /SoC ...power how humans and technology work together across the physical and digital worlds. These solutions provide customers with… more
- Cisco (San Francisco, CA)
- … and verification, digital signal processing, memory and custom library development, physical design , DFT, signal integrity, and advanced packaging. Work with ... (eg, Python, Perl, TCL) for automation. + Familiarity with ASIC /SoC design flow including synthesis, place &... verification methodologies (eg, UVM, SystemVerilog) + Understanding of physical design and DFT ( Design … more
- Cisco (San Jose, CA)
- **Sr. ASIC Engineer ** The application window is...refining design and timing constraints for seamless physical design closure. As part of this ... provide. You will work with exceptional talent with vast ASIC design and development expertise. With Cisco... team who oversees fullchip SDCs and works with physical design and DFT teams to close… more
- Cisco (San Jose, CA)
- …to improve verification efficiency, quality, and coverage at scale + Influence ASIC architecture and design to enable robust verification and high-quality ... networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a...power how humans and technology work together across the physical and digital worlds. These solutions provide customers with… more
- Broadcom (San Jose, CA)
- …and route, clock methodology, power planning and analysis, timing closure, signal integrity and physical design checks. + Participate in large complex design ... Candidate Account, please Sign-In before you apply.** **Job Description:** ASIC Implementation Engineer with demonstrated expertise in...latest technology nodes, lead one or more disciplines in design closure as part of the design … more
