- Compunnel, Inc. (Mountain View, CA)
- A leading technology firm seeks a skilled FPGA Verification Engineer in Mountain View. This role involves verifying FPGA designs with advanced ... methodologies and requires strong expertise in SystemVerilog, UVM , and debugging skills. The ideal candidate will develop verification plans, utilize… more
- SQL Pager LLC (San Jose, CA)
- A leading company in semiconductor technology is seeking a VLSI Verification Engineer who will collaborate with design teams and develop verification ... environments. The ideal candidate has a strong background in ASIC/ FPGA verification , advanced knowledge of System Verilog, and is skilled in both C/C++ and… more
- Kubelt (Alameda, CA)
- …block diagrams, interface definitions, and design specifications Develop and enhance FPGA verification workflows, utilizing simulation and formal verification ... Foundry. We are seeking a highly skilled and motivated FPGA /Firmware Engineer to join our team and...industry or other highly regulated environments Experience with RTL verification frameworks (eg, UVM , cocotb) Exposure to… more
- Compunnel, Inc. (Mountain View, CA)
- The FPGA Verification Engineer will be responsible for verifying FPGA designs using advanced methodologies and tools. This role requires strong expertise ... deliverables. Key Responsibilities Develop and execute verification plans for FPGA designs using SystemVerilog and UVM methodology. Utilize industry-standard… more
- Amazon (San Francisco, CA)
- …with scan insertion tools, ATPG, gate ‑level simulations. Advanced knowledge of verification platforms including UVM test bench, FPGA , and emulator ... 3+ years of experience in a semiconductor company as a DFT engineer . Preferred Qualifications Experience with chip design, Verilog and System Verilog. Experience… more
- Mythic, Inc. (Palo Alto, CA)
- …(Karnataka, India). About This Role We are seeking a Director / Principal Engineer of Digital Design Verification to provide technical and strategic leadership ... boot, security, clocking, reset, and DFT features. Define and enforce UVM -based verification methodologies. Drive adoption of: Coverage-driven verification… more
- Advanced Micro Devices (San Jose, CA)
- …collaborative, and inclusive of diverse perspectives. AMD together we advance_ The Role As a verification engineer in the AECG Group, you will help bring to life ... cutting-edge FPGA , ASICs for variety of target customers. As a...software driver use cases Code IP or SS level UVM based testbenches, verification components - monitors,… more
- SQL Pager LLC (San Jose, CA)
- …years or MSEE with 1+ years experience Advanced knowledge of standard ASIC/ FPGA verification flows including simulation, testbench development, and post silicon ... and understand specifications / architectures / micro-architectures Define and review verification test plans Develop block level and chip level verification… more
- Analog Group (San Jose, CA)
- …and network equipment. Job Function: Digital Design (RTL design): ASIC or FPGA from concept to implementation. Digital Verification : Development test plans, ... The Sr. Digital Design Engineer candidate must have demonstrated success in digital...target schedule. Qualifications: 3-5 years' experience in design plus verification of ASIC or FPGA . Strong knowledge… more
- Microsoft Corporation (Mountain View, CA)
- …manage and optimize the Cloud infrastructure. We are looking for a **Senior Verification Engineer ** to join our team! **Responsibilities** + Perform pre-silicon ... verification for complex IP, including creating testplans, developing Universal Verification Methodology ( UVM ) components and environments from scratch,… more
- Broadcom (San Jose, CA)
- …verification tasks such as: verification environment development using modern verification techniques (System Verilog and UVM ); designing verification ... flows and DV methodologies + Strong working knowledge of object oriented verification languages (OVM, UVM , etc.), C/C++, Perl, and scripting skills. +… more
- Microsoft Corporation (Mountain View, CA)
- …will manage and optimize the Cloud infrastructure. We are looking for a **Senior Verification Engineer ** to join the team. **Responsibilities** The role will be ... verification methods + Experience in RTL design for FPGA or emulation + Experience in Assembly, startup code...with test plan definition + Substantial background in creating UVM Test Benches, developing tests, and debugging designs +… more
