- Google (Fremont, CA)
- Senior Silicon Bringup and Test Lead, Raxium _corporate_fare_ Google _place_ Fremont, CA, USA **Advanced** Experience owning outcomes and decision making, solving ... 10 years of experience in analog circuit design, including simulation and verification . + Experience working with relevant Electronic Design Automation (EDA) tools… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …DDR4/5, LPDDR4/5/5X, HBM2/3, GDDR6* Perl/Python Scripts* Experience on memory subsystem verification and/or performance analysis* Strong knowledge of ASIC flow, ... to make an impact on the world of technology. Senior Applications Engineer - DDR Design IPJob Location: San...use your knowledge of different memory interface standards to architect memory solutions for customers using Cadence DDR IP.… more