- Google (Fremont, CA)
- …detail and problem-solving skills. + Effective communication and collaboration abilities. As a Silicon Layout Engineer , you will be responsible for ... practical experience. + 8 years of experience in physical layout design and verification. + Experience in industry-standard ...start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its… more
- Google (Fremont, CA)
- …cycle for an entire analog integrated circuit, including schematic capture, simulation, layout oversight, and ultimately taking the design through to full chip ... display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with… more
- Power Integrations (San Jose, CA)
- Job Description: The Staff Silicon Level Failure Analysis Engineer will perform device level failure analysis to support RMA and customer issues. ... required. Ability to interpret system level schematics, the IC level schematics, and IC layout of CMOS and bipolar devices is required. + Verbal and reading, skills… more