- Google (Mountain View, CA)
- …technology process nodes. + Experience with ASIC design flows and methodology of static timing analysis . + Experience in extraction of design ... Google (https://careers.google.com/benefits/) . + Be responsible for delivering System-on-Chip (SoC) Static Timing Analysis . + Define SoC timing signoff… more
- Microsoft Corporation (Mountain View, CA)
- …+ OR equivalent experience. + 8+ years of experience in Physical Design, specifically Static Timing Analysis and Convergence domains. + 8+ years of ... the Cloud infrastructure. We are looking for a **Principal Timing /STA Engineer ** to join the team. **Responsibilities**...drive timing constraints and methodology. + Conduct timing analysis and sign-off for critical paths,… more
- Cisco (San Jose, CA)
- ASIC Design Engineer - Design & Timing Constraints...development in functional and test modes + Experience in Static Timing Analysis and prior ... of our systems, leveraging the latest technology. We're seeking a talented ASIC engineer with a proven track record in high-performance products, ready to make a… more
- Cisco (San Jose, CA)
- …with block/full chip SDC development in functional and test modes. + Experience in Static Timing Analysis and prior working experience with STA tools ... ASIC Design Technical Leader - Design & Timing Constraints Focus Apply (https://jobs.cisco.com/jobs/Login?projectId=1432242) + Location:San Jose, California, US +… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …innovators who want to make an impact on the world of technology. Responsibilities; Perform Static timing analysis , glitch, noise analysis using Tempus ... seminars within Cadence and customer sites. Requirements; 10+ years of experience in Static timing analysis , Individual should be able to lead and execute… more
- Arrow Electronics (San Jose, CA)
- …with **block/full chip SDC development** in functional and test modes. + Experience in ** Static Timing Analysis ** and prior working experience with STA tools ... **Position:** SDC Engineer (eInfochips Inc) **Job Description:** **Position: SDC ...with physical design and DFT teams to close **fullchip timing ** in multiple timing modes. + Option… more
- Cisco (San Jose, CA)
- …working with Verilog or System Verilog programming skills + Experience with simulators/synthesis/ static timing constraints and related tools (eg, VCS, DC, ... , performance, and power requirements. + Contribute to full chip integration and timing methodology/ analysis . + Develop and analyze functional coverage. + Help… more
- CDM Smith (San Francisco, CA)
- …of Science in Civil Engineering with a Structural Focus. - Professional Structural Engineer license. - Experience with analysis and design of reinforced concrete ... codes and application to design situations. - Strong theoretical background in static and dynamic analysis of hydraulic structures and appurtenances with… more
- Microsoft Corporation (Mountain View, CA)
- …optimize the Cloud infrastructure. We are looking for a **Senior Silicon Logic Design Engineer ** to join the team. **Responsibilities** In this role, you will be an ... functional block RTLs into SoC RTL + Performing design quality checks such as timing closure, lint, CDC, synthesis, and low power intent + Collaborating with the… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …higher) in Computer/Electrical Engineering + Strong knowledge of Digital Design Fundamentals and Static Timing Analysis + Prior experience with IC digital ... of technology. As an expert Digital Implementation Field Applications Engineer (AE) , you will work side-by-side with our...implementation flows - Synthesis, Place and Route, IR Drop, Timing Signoff + Prior experience with Cadence tools (Genus,… more
- Advanced Energy (Redwood City, CA)
- …and GUI including floor planning / optimization of design. + In-depth understanding of timing analysis and closure, both static and dynamic. Good ... Firmware Engineer II **ABOUT ADVANCED ENERGY** Advanced Energy (Nasdaq:...schedule, and technical constraints. + Perform technical review, design analysis , development and selection of hardware for mission critical… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …will be focused on: + Enhancing and expanding the existing tools' architecture to cover timing analysis + Creating new frameworks for analysis of effects ... expert R&D team creating technologies and products that enable static and dynamic transistor level analysis of...EDA tools and one or more of transistor level timing , power, noise, aging, reliability, and emir analysis… more
- Broadcom (San Jose, CA)
- …to debug LVS/DRC issues at the chip and block level.** + **Experience with CDC, static timing analysis methodologies and relevant tools.** + **Exposure to ... is looking for a senior level ASIC physical design engineer . In this highly visible role, you will be...must be familiar with Virtuoso, Caliber & Redhawk (power analysis ) tools.** + **Good understanding of design tape-out to… more
- Broadcom (San Jose, CA)
- …implementation spec writing from marketing/system requirements, RTL design and verification, synthesis, static timing analysis . You will either be ... Verilog/VHDL coding and Lint tools * Synthesis using Synopsys tool suite * Timing Analysis using Synopsys Primetime tool * Formal Verification * DFT concepts of… more
- Broadcom (San Jose, CA)
- …principles such as sampling, noise shaping and filtering. + Experience in synthesis, CDC, static timing analysis . + Exposure to SDF annotated simulations ... please Sign-In before you apply.** **Job Description:** High Speed RTL Design Engineer Qualifications include: + MS or PhD in Electrical Engineering or Computer… more
- Broadcom (San Jose, CA)
- …initial floor plan. 4). Develop Verilog RTL. logic synthesis, physical implementation constraints, static timing analysis . 5). Work directly with the ... physical implementation team from initial floor planning to final timing closure. **Job Requirements:** The successful candidate will satisfy the following… more
- Broadcom (San Jose, CA)
- …power, and cost over the project lifetime.** + **Experience in synthesis, CDC, static timing analysis .** + **Exposure to SDF annotated simulations ... with good understanding of parasitic delays.** + **Experience in design management with detailed knowledge of development methodologies, design flows including EDA integration, foundry PDK and associated collaterals.** + **Strong analytical thinking and… more