- Google (Mountain View, CA)
- …embedded SRAM design (cell and macro) and characterization. + Experience in CMOS technology and device characterization, process integration and SPICE ... + Experience in product-level testing in Static Random Access Memory (SRAM) including yield and parametric evaluation. + Excellent...(PDPPA) team to evaluate PPA accounting both logic and memory at IP level. + Work with the IP… more
- NVIDIA (Santa Clara, CA)
- …intelligence. We are seeking an innovative senior timing and VF Methodology engineer to develop pioneering timing sign-off strategies for next-generation GPUs and ... 3+ years' experience in ASIC Design and Timing. + Knowledge of device physics, STA methodology. + Good understanding of mathematics/physics fundamentals of… more