- Broadcom (San Jose, CA)
- …please Sign-In before you apply.** **Job Description:** **Broadcom is looking for a high - speed DSP SerDes RTL designer. Qualifications include:** ... Computer Engineering with 6+ years of experience in high speed ADC based SerDes RTL design.** + **Proficient with Verilog-HDL/System Verilog coding for… more
- Broadcom (San Jose, CA)
- …applications.** + **Experience as a Lead digital designer for chip and platform for high bandwidth/ high speed SerDes applications in advanced modulation ... integration, foundry PDK and associated collaterals.** + **Deep understanding of high - speed optical/electrical interconnect architectures such as 200G per lane… more
- NVIDIA (Santa Clara, CA)
- …design and adaptation algorithms (FFE, DFE, CTLE, CDR, offset cancellation), understanding of high - speed SerDes I/O digital design, with knowledge of ... As a Senior Digital Design Manager in our Mixed-Signal High - Speed I/O SerDes group, you'll...Verilog or SystemVerilog, logic design, and circuit modeling in RTL for mixed-signal blocks + Strong background in custom… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is looking for a Senior Design Engineer for our Coherent High Speed Interconnect team! For two decades, NVIDIA has pioneered visual computing, the art and ... be working on architecture and design of our state-of-the-art high speed coherent interconnects (NVLINK-C2C) for our...such as Memory (DDR, LPDDR etc..) , PCIE , SerDes + Experience and knowledge in architecture, RTL… more
- NVIDIA (Santa Clara, CA)
- …and intelligence. Make the choice to join us today. As a member of our Mixed-Signal high - speed I/O SerDes group, you'll be working on NVDIA's latest ground ... be consumed by standard as well as industry-leading proprietary high - speed protocols, and will serve as one...specification and refine adaptation algorithms. You'll then implement the RTL in SystemVerilog, define test cases that will deeply… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …team of engineers * Physical Layer and Protocol layer experience on AT LEAST ONE High speed SERDES on Ethernet/ PCIe/CXL/UCIe/ * Debug skills and Experience ... in Schematic and layout level. Familiarity with peripheral chips, high speed interface design techniques, Signal and...qualification & specification + Expert level knowledge in Verilog RTL coding for FPGA, python,C/C++ The annual salary range… more