- Qualcomm (Santa Clara, CA)
- …SoC Implementation Team is looking for skilled engineers to focus on timing constraints development, power analysis, STA , and timing closure for ... This is an excellent opportunity to join the Snapdragon implementation team, which is responsible for SoCs in sub-3nm...and low-power multi-voltage domain crossings, and signoff with static timing analysis. + Collaborate closely with RTL design… more
- Microsoft Corporation (Sunnyvale, CA)
- …semiconductor designs. + Collaborate with design , implementation , and physical design teams to define and drive timing constraints and methodology. + ... the Cloud infrastructure. We are looking for a **Principal Timing / STA Engineer** to join the team. **Responsibilities**...targets. + Work closely with cross-functional teams to resolve timing issues, optimize design performance, and meet… more
- Amazon (Sunnyvale, CA)
- …that is powering the latest generation of Echo devices is looking for a Senior SoC Design - STA Engineer to continue to innovate on behalf of our customers. We are ... Includes definition and development of signoff methodology and corresponding implementation solution * Flow for STA , Crosstalk...& Route and other local/remote teams to address the design challenges in the context of timing … more
- Qualcomm (Santa Clara, CA)
- …you will work with microarchitecture and RTL design team to develop timing constraints, drive implementation of the designs to meet aggressive power, area ... Design Timing Engineer,... automation using TCL/Perl/Python. + Familiar with digital flow design implementation RTL to GDS : ICC, Innovous… more
- Google (Mountain View, CA)
- …silicon timing closure and chip integration. + Experience with STA signoff constraint authoring for full-chip level, tapeout signoff requirements, checklists, ... in state-of-the-art technology process nodes. + Experience with ASIC design flows and methodology of static timing ...full chip timing constraint creation and validation, timing signoff checklist criteria, perform full chip STA… more
- NVIDIA (Santa Clara, CA)
- …and/or full chip level. + Help in driving frontend and backend implementation including synthesis, equivalence checking, floor-planning, timing constraints, ... timing and power convergence, and ECO implementation . + Work in a cross-functional environment interacting with... Timing + Hands-on experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints… more
- NVIDIA (Santa Clara, CA)
- …in Physical design / Timing . + Experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints generation and management, and ... as timing constraints, timing analysis, timing convergence, and ECO implementation . What we...multiplexed scan logic and constraints. + Expertise in physical design , optimization, and ECO implementation eg cell… more
- Google (Sunnyvale, CA)
- …about benefits at Google (https://careers.google.com/benefits/) . + Debug and resolve common Static Timing Analysis ( STA ) or design rule issues like ... + Experience writing, reviewing and verifying complex TCL constraints for static timing analysis. + Experience in extraction of design parameters, QoR… more
- NVIDIA (Santa Clara, CA)
- …or MS (or equivalent experience) with 3+ years' experience in ASIC Design and Timing + Hands-on experience in STA tools, ECO implementation , and ... timing including setting up timing constraints, timing analysis and closure, ECO implementation , and...to collaborate with cross-functional teams. + Strong understanding of timing and physical design fundamentals Ways to… more
- Qualcomm (Santa Clara, CA)
- …for all Qualcomm Business Units. Minimum Skill/Experience: + 2-10 yrs experience in Physical Design and timing signoff for high speed cores. + Should have good ... **Experience in leading block level or chip level Physical Design , STA and PDN activities** . +...Work independently in the areas of RTL to GDSII implementation . + Ability to collaborate and resolve issues wrt… more
- Meta (Sunnyvale, CA)
- …levels. From microarchitecture definition and RTL implementation to synthesis and timing closure, fundamentals in digital design will enable you to ... collaboration with Digital Verification (DV) 3. Support back end physical design (PD) through STA and SDCs 4. Drive IP/sub-system micro-architecture and RTL … more
- SpaceX (Sunnyvale, CA)
- …will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design , validation, product engineering, ASIC implementation ). In this ... voltage drop, logic equivalency and other signoff checks) + Develop/improve physical design methodologies and automation scripts for various implementation steps… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Backend Digital Design Implementation and Signoff including Place and Route, Design Closure, and timing /power signoff + Guide customers on how to best ... Electrical, Engineering, or related field + 12+ years of design /EDA experience (methodology, flow, implementation , RTL2 GDS)...EDA tools including Place and Route, IR Drop, backend design timing and power closure + Experience… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. What you will be doing: + Developing innovative physical design methodologies for implementation of GPU, CPU and SOCs, with ... tree synthesis methods and techniques + Strong background in STA , extraction, timing and RC correlation +...timing and RC correlation + Good understanding of design rules in advanced nodes and their impact on… more
- NVIDIA (Santa Clara, CA)
- …member of the DFX methodology team, you will be responsible for the architecture, design , implementation and verification of fuse controller and other DFT IPs ... architects, other designers, pre- and post-silicon verification teams, synthesis, timing and back-end teams + Work on generating test...exposure to cross functional areas including RTL & clocks design , STA , place-n-route and power, to ensure… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Digital Design Implementation & Signoff including Synthesis, Place and Route, Design Closure, and timing /power signoff + Guide customers on how to best ... related experience in design and EDA (Digital Implementation /Signoff) + Understands ASIC Design implementation...+ Experience with EDA tools in the IC digital implementation & signoff flows ( STA tools) +… more