- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior Physical Design Methodology Engineer (s) - PPA Fusion ... technology-focused company. What you will be doing: + Developing Efficient physical design methodologies for implementation of graphics processors and SOCs. +… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior Physical Design Methodology Engineer (s) to join our ... impact in a technology-focused company. What you will be doing: + Developing physical design methodologies for implementation of graphics processors and SOCs. +… more
- Amazon (Cupertino, CA)
- …of machine learning and AI services for our customers' businesses. We are seeking experienced Physical Design Engineer to build the next generation of our ... today. Key job responsibilities - You will create and support innovative physical design methodology and CAD flows. - Develop cloud infrastructure to… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. What you will be doing: + Developing innovative physical design methodologies for implementation of GPU, CPU and SOCs, with ... PPA (Power, Performance, Area) and runtime improvement of the physical design flow on advanced technology nodes...with internal and external partners to drive tool and methodology improvements to deliver best-in-class PPA solutions across all… more
- NVIDIA (Santa Clara, CA)
- …devices for high-speed optical interconnect and sensing applications. + Developing physical design methodologies for implementation of graphics processors and ... driving cars. Come join us in our mission to Engineer the next generation of best-in-class products. Our teams...and creative solutions to the state of the art physical design problems that are needed for… more
- NVIDIA (Santa Clara, CA)
- …intelligence. We are seeking an innovative senior timing signoff and constraint methodology engineer to develop pioneering timing sign-off strategies for ... next-generation GPUs and SoCs. In this role, you'll develop methodology and flows to validate timing constraints from RTL...clock domains across hierarchical boundaries). + Collaborate with RTL, physical design , and verification teams to drive… more
- NVIDIA (Santa Clara, CA)
- We are looking for a Senior CPU Implementation Methodology Engineer to join our VLSI team! If you are looking for a challenging and exciting role and you are a ... from Synopsys (DC/FC), Cadence (Genus/Innovus) + Strong understanding of physical design implementation eg: physical ...out from the crowd: + Prior CPU experience in physical implementation methodology + Proficiency in Perl,… more
- Qualcomm (Santa Clara, CA)
- …create designs that push the envelope on performance, energy efficiency and scalability. As CPU Physical Design CAD engineer , you will build and support the ... flows, and resolve project-specific issues + Work closely with worldwide CPU physical design teams, and provide methodology guidance, tools/flows support and… more
- Qualcomm (Santa Clara, CA)
- …to define, develop and drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer , you will work with microarchitecture and RTL ... and also useful in enabling CPU timing infrastructure and methodology impacting multiple CPU projects in Qualcomm. You will...out the root cause of timing miscorrelation at different design levels in functional and test mode, propose solutions.… more
- Qualcomm (Santa Clara, CA)
- …good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology . + Masters/Bachelors Degree in ... smarter, connected future for all. As a Qualcomm CPU Engineer , you will lead innovative Central Processing Unit (CPU)...Business Units. Minimum Skill/Experience: + 2-10 yrs experience in Physical Design and timing signoff for high… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer to join our dynamic and growing team. If ... intelligence. What you'll be doing: + Drive next generation physical design work to achieve best in...of circuits and SPICE, as well as experience in methodology and/or flow development and automation. NVIDIA is widely… more
- Broadcom (San Jose, CA)
- …before you apply.** **Job Description:** **Broadcom is looking for a senior level ASIC physical design engineer . In this highly visible role, you will ... and high speed clock constraints and specification.** + **Good understanding of physical design verification methodology to debug LVS/DRC issues at the chip… more
- Qualcomm (Santa Clara, CA)
- …for physical design related issues is a must. Deep understanding of physical design flow and methodology is preferred. Minimum Requirements: - 2+ ... will be working on low power next generation Wifi subsystem related Physical design implementation. You will also be actively involved in Floor Planning (FP),… more
- NVIDIA (Santa Clara, CA)
- …timing paths through ECOs including crosstalk and noise analysis. + Expertise in physical design and optimization eg, placement, routing, cell sizing, buffering, ... We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If...experience to improve timing convergence flows working with the methodology teams. What we need to see: + BS… more
- Cisco (San Jose, CA)
- ASIC Design Engineer - Design & Timing...in refining design and timing constraints for seamless physical design closure. As part of this team, ... of what's possible! **Your Impact** You are a diligent Design /SDC Engineer with strong analytical skills and... team who oversees fullchip SDCs and works with physical design and DFT teams to close… more
- Meta (Sunnyvale, CA)
- …create as part of a world-class engineering team. **Required Skills:** Package Design Engineer Responsibilities: 1. Drive chip-package-system co- design by ... interface and PDN, create simulation models and develop simulation methodology for SIPI design 7. Lead SIPI...Input/Output Physical Layer (IO PHY), SI/PI and physical design **Minimum Qualifications:** Minimum Qualifications: 13.… more
- Cisco (San Jose, CA)
- Senior ASIC Design Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1431806) + Location:San Jose, California, US + Area of InterestEngineer - Hardware ... functional coverage. + Help define, evolve, and support our design methodology . + Collaborate with the verification...and close code coverage. + Work closely with the physical design team to close design… more
- NVIDIA (Santa Clara, CA)
- We are now looking for an ASIC Design Efficiency Engineer . NVIDIA is seeking extraordinary methodology engineers to design hardware accelerators and ... of the art performance and efficiency. + Understand the design and implementation, develop methodology and infrastructure...the crowd: + Pipeline processor or deep learning accelerator design /architecture experience + Low power or physical … more
- Palo Alto Networks (Santa Clara, CA)
- …will provide technical leadership, collaborate extensively with world-class verification and physical design engineers to hit aggressive performance, power, and ... and add design -for-debug features + **Collaborate** effectively with physical design teams, including reviewing synthesis/timing reports, rewriting RTL… more
- Google (Sunnyvale, CA)
- …of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a SoC Design Engineer , you will join a team working on SoC-level ... and control subsystem, also participate in developing infrastructure and methodology that form the foundation of our SoCs (ie,...to verify and debug RTL designs. + Work with physical design teams to ensure design… more