- SpaceX (Sunnyvale, CA)
- SOC/ASIC Synthesis & Front-End STA Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... goal of enabling human life on Mars. SOC/ASIC SYNTHESIS & FRONT-END STA ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building… more
- Arrow Electronics (San Jose, CA)
- **Position:** STA Engineer **Job Description:** POSITION SUMMARY * Proven experience in constraints (Func/Test) handling, block and top level static timing ... on Automation (Perl/Tcl/Awk/Python) * Able to provide technical guidance to Junior Engineer * Good in communication skill EDUCATION BACKGROUND A Bachelor's degree in… more
- Qualcomm (Santa Clara, CA)
- …help create a smarter, connected future for all. As a Qualcomm Hardware Engineer , you will plan, design, optimize, verify, and test electronic systems. Qualcomm ... reduce power. Lead Static Timing Analysis, work closely with CAD teams on PD STA flow integration and updates; Lead Timing Closure with Automated ECO tools, flows… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …constraints, advanced OCV/SOCV concepts, derates, PBA timing, Distributed, Concurrent and Hierarchical STA flows. . Work efficiently with R&D and customer to enable ... basic understanding of Place and route, power analysis. Related tools/Keywords; PrimeTime, STA , Quantus #LI-MA1 The annual salary range for California is $138,600 to… more
- Amazon (Sunnyvale, CA)
- …is powering the latest generation of Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate on behalf of our customers. We are a part of ... development of signoff methodology and corresponding implementation solution - Flow for STA , Crosstalk Delay and Crosstalk Noise analysis for digital ASIC/SoCs. -… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …to enable new and differentiating technologies.. + In this role, the Solutions Engineer (SE) is expected to work both independently and in collaboration with other ... team members to address customer issues and to identify new opportunities or Risk that are linked to those activities + The SE will interact with Product Engineering/RnD Team as well as Key Technologists at customer site to develop and enable new… more
- Microsoft Corporation (Santa Clara, CA)
- We are looking for a **Physical Design Methodology Engineer ** . As part of our DPU silicon team, you will help lead the way for our cutting-edge ASICs, supporting ... flows and automation for critical tools (place & route, extraction/ STA , physical verification, etc); deploy and test new flows;...including hands-on experience in synthesis, place & route, and STA . + 4+ years of experience with Synopsys design… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role in raising ... generation of CPU, GPU or SOC designs. + Owning STA of large subsystems and full chip designs or...timing issues, timing constraints and clocking. + Expertise in STA tools and methodologies for timing closure with a… more
- NVIDIA (Santa Clara, CA)
- …methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If you are problem solver and ... in Physical design/Timing. + Experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints generation and management, and timing convergence. +… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Physical Design and Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part of ... and Timing + Solid experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints generation and management, and timing convergence. + Hands… more
- NVIDIA (Santa Clara, CA)
- …are now looking for a motivated Senior ASIC Physical Design PPA (Performance, Power, Area) Engineer to join our dynamic and growing team. If you are looking for a ... physical DBs (databases) and drive new ideas + Hands-on experience in STA and timing closure including multi-mode analysis, timing constraints generation and… more
- ManpowerGroup (San Jose, CA)
- …innovate in an unparalleled time to market. **You Are:** An experienced SoC Integration Engineer **The Work:** The ideal candidate can help along the design flow to ... DFT checks, support regression and release process and analyze STA timing results. **Here's what you need:** + A...+ A minimum of 3 years of experience with STA (Static Timing Analysis) and PrimeTime and related timing… more
- NVIDIA (Santa Clara, CA)
- …in Physical design/Timing + Experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints generation and management, and timing convergence + ... eg cell sizing, buffering, VT swap + Hands-on knowledge of industry standard Timing/ STA EDA tools + Proficiency in programming and scripting languages, such as TCL,… more
- Qualcomm (Santa Clara, CA)
- …to ensure DFT DRCs are fixed. + Analyzing and meeting ATPG coverage goals + Owns STA constraints and work with STA team to resolve timing violations + owns IDDQ ... constraints generation and validation + Working independently in the team to solve problems, enable his team to deliver on time with high quality + Responsible for deliverables of certain aspects of SoC DFT execution + Responsible for pattern verification and… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …level simulations to verify functionality. + Perform and help debug Synthesis/ STA scripts/constraints. + Participate in development of Application notes, Training ... + Verilog RTL design and gate level verification experience. + Synthesis and STA experience, back-end experience is a plus + Familiarity with industry standard DFT… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Compiler) + Experience with EDA tools in the IC digital implementation & signoff flows ( STA tools) + Strong STA and SDC debugging abilities are required. + Low ... power analysis, Clock design/analysis and hands-on 7/5nm technology node experience a plus. + Automation skills using Perl, Tcl and shell scripting essential + Strong analytical & analysis skills covering digital implementation is critical. + Proven track… more
- SpaceX (Sunnyvale, CA)
- Principal SOC/ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... goal of enabling human life on Mars. PRINCIPAL SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a DFT Methodology Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of ... to cross functional areas including RTL & clocks design, STA , place-n-route and power, to ensure we are making...are growing fast. If you're a creative and autonomous engineer with real passion for technology, we want to… more
- Google (Sunnyvale, CA)
- …Experience in physical design areas such as synthesis, place and route, STA , formal verification, or power analysis. Preferred qualifications: + Experience scripting ... that power all of Google's services. As a Hardware Engineer , you design and build the systems that are...millions of Google users. As a SoC Physical Design Engineer , you will collaborate with Functional Design, Design for… more
- NVIDIA (Santa Clara, CA)
- …to join us today. We are now looking for a highly motivated DFT Engineer to join this multifaceted and innovative hardware team at NVIDIA. Our Design-for-Test ... vendor tools. + Good exposure to multiple domains including RTL & clocks design, STA , place-n-route and power, to ensure we are making the right trade-offs. +… more