- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Power Engineer ! NVIDIA is seeking extraordinary power engineers to design hardware accelerators and processors ... are expected to understand the design and implementation, develop power metrics and drive power reductions +...want to hear from you. Come, join our GPU ASIC team and help build the real-time, cost-effective computing… more
- The Boeing Company (Mountain View, CA)
- …Missiles & Weapons; Strike, Surveillance and Mobility; and Autonomous Systems). As an ASIC /FPGA Engineer on the Boeing Electronic Products team you will develop ... and/or FPGA Design and Verification Engineers** (Experienced, Lead, or Senior ) to join us as part of our Boeing...determine the optimal parts, weighing Schedule, Cost, Risk, Area, Power (SCRAP) vs. performance + Implement FPGA/ ASIC … more
- Cisco (San Jose, CA)
- Senior ASIC Design Engineer ...+ Implement Verilog RTL to meet timing, performance, and power requirements. + Contribute to full chip integration and ... Cisco's silicon team provides an outstanding, unique experience for ASIC engineers by combining the resources offered by a...innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Floorplan Design Engineer ! NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the ... chip development. + Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities +… more
- Palo Alto Networks (Santa Clara, CA)
- …create an environment where we all win with precision. **Your Career** As a Design Verification engineer on the ASIC team, you will ensure that the ASICs in our ... few! At Palo Alto Networks, we believe in the power of collaboration and value in-person interactions. This is...in close collaboration with system architects, software engineers, and ASIC designers + Define new tools and methodologies to… more
- NVIDIA (Santa Clara, CA)
- …design tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Synthesis Engineer to join our dynamic and growing ... intelligence. What You'll Be doing: + As a Front-End ASIC Synthesis Engineer , you will own RTL...timing, area, congestion tradeoffs + Drive timing closure and power /area optimization across multiple design blocks + Work with… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer . NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... team, you will implement, document and deliver high performance, area and power efficient RTL to achieve design targets and specifications. + Analyze architectural… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world's leading SoC's and GPU's. This position offers the ... and Digital Systems design. + A deep understanding of ASIC design flow including RTL design, verification, logic synthesis,...the challenge of crafting the highest performance & lowest power silicon possible? If so, we want to hear… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At...as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer / Senior : $170,000.00 - $230,000.00/per year Your actual… more
- NVIDIA (Santa Clara, CA)
- The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design Verification. The NVIDIA Clocks Team ... reset logic to various units in SOC and GPU ASIC . The complexity of the clocks and resets design...verification to deliver a bug free clocks design to power our product lines ranging from Data Centers, Consumer… more
- NVIDIA (Santa Clara, CA)
- …design tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! ... constraints. + Finding the right tradeoffs and balance between frequency and power /area/congestions/yield/etc. + Work on all aspects of DFT/Test timing such as… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer - DFX NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power , to ensure we are making the right trade-offs + Experience in Silicon… more
- Palo Alto Networks (Santa Clara, CA)
- …deliver the digital logic that powers our next-generation firewall platforms. As a Senior Principal Engineer , you will take end-to-end ownership of complex ... few! At Palo Alto Networks, we believe in the power of collaboration and value in-person interactions. This is...members. This role requires a deep technical background in ASIC design for networking applications and the ability to… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer to join our dynamic and growing team. If ... closure of high-performance designs with a focus on improving PPA (Performance, Power , Area). + Good understanding of hardware architecture and RTL/logic design for… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation. + Work in a cross-functional… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... up with timing closure strategy, creating timing constraints, driving timing and power convergence, as well as ECO implementation + Apply knowledge and experience… more
- NVIDIA (Santa Clara, CA)
- …and timing methodologies. + Finding the right tradeoffs and balance between power /area/congestions/etc. What we need to see: + BS (or equivalent experience) in ... 5+ years' experience or MS (or equivalent experience) with 3+ years' experience in ASIC Design and Timing + Hands-on experience in STA tools, ECO implementation, and… more
- Cisco (San Jose, CA)
- ASIC Design Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1441220) + Location:San Jose, California, US + Area of InterestEngineer - Hardware + ... in the world. You will engage in dynamic collaboration with Senior micro-architects, designers, verification engineers and interact with cross-functional software… more
- Amazon (Cupertino, CA)
- …to Global 500 companies trust our robust suite of products and services to power their businesses. Diverse Experiences AWS values diverse experiences. Even if you do ... scale and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while… more
- Amazon (Sunnyvale, CA)
- …provide low-latency, high-speed broadband connectivity. Come work at Amazon! The Role: As Senior CAD Engineer you will be responsible for installing and ... Digital design RTL2GDS experience with emphasis on methodology and best practice - Power estimation and optimization - Back end tool experiences a plus, including… more