- Cadence Design Systems, Inc. (San Jose, CA)
- …on the world of technology. Cadence Design Systems is looking for a highly motivated software or digital IC design engineer to work with the Innovus routing team ... and Tcl scripting is preferred + Experience in P&R software tool usage is a plus + Excellent programming...tool usage is a plus + Excellent programming and software engineering skills + Experience with UNIX and/or LINUX… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …our customers, our communities, and each other-every day. Role As a Principal C++ Software Engineer , you will: + Innovate and develop cutting-edge solutions to ... 1 year of related experience. + Experience with EDA applications such as synthesis, place and route , timing, and optimizations. + Strong programming skills in… more
- LinkedIn (Mountain View, CA)
- …for the kernel development lifecycle (including but not limited to synthesis, place -and- route , timing analysis, validation and verification) and deploy them on ... optimize performance across algorithms, AI frameworks, data infra, compute software , and hardware. In this role, you will be...the large scale AI models. As a Sr. Staff Engineer on the AI Infra team, you will play… more
- Qualcomm (Santa Clara, CA)
- …+ Develop, integrate and release new features in our high-performance place -and- route CAD flow + Architect and recommend methodology improvements ... energy efficiency and scalability. As CPU Physical Design CAD engineer , you will build and support the world's best...Computer Science + Ten+ years of hands-on experience in place -and- route of high-performance chips - either in… more
- Siemens (Fremont, CA)
- …Synthesis solutions. College-level exposure to FPGA hardware design through RTL Synthesis and Place & Route is key. AMD/Xilinx or Intel/Altera, Lattice, or ... Job Family: Software Req ID: 461784 Company: Siemens EDA Job...rework RTL FPGA designs to improve end results in Place & Route + Create and deliver… more
- Qualcomm (Santa Clara, CA)
- …goals using industry standard tools/flows. Minimum Requirements + Proficiency in synthesis, place and route , and signoff timing/power analysis. + Expertise in ... needs of the server/compute/mobile platforms. As a CPU PD Engineer , you will work with microarchitecture, RTL design and...plus + Solid understanding industry standard tools for synthesis, place & route and tape out flows.… more
- Siemens (Santa Clara, CA)
- Job Family: Software Req ID: 468177 Siemens EDA is a global...is looking for an experienced Place & Route user or Applications Engineer to play a ... technology leader in electronic design automation software . Our software tools enable companies around...the industry's rapidly expanding interest in Aprisa, the Siemens Place & Route offering. Since the acquisition… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …teams solve problems. We are seeking individuals with experience in Digital Synthesis, Place and Route and Signoff Analysis. Where is this returnship located: ... to re-enter the workforce as a Physical Design Application Engineer after taking a career break for caregiving? Who...in the Application Engineering field spanning across Digital Synthesis, Place and Route and Signoff Analysis. How… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …chip design platforms. As Product Engineer , you will be a source of technical place and route expertise to Cadence customers and to R&D. You are a motivated ... world of technology. This opportunity is for a Product Engineer in the Digital and Signoff Group (DSG) at...influence the development of software tools for advanced… more
- SpaceX (Sunnyvale, CA)
- …physical implementation steps (eg synthesis, floorplanning, power/ground grid generation, place and route , timing, noise, physical verification, ... SOC/ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was...users to connect within minutes of unboxing, and the software that brings it all together. We've only begun… more
- Qualcomm (Santa Clara, CA)
- …role involves good understanding of functional and test (DFT) mode constraints for place and route , floorplanning, power planning, IR drop analysis, cell ... SOC and core design team. As a physical design engineer you will innovate, develop, and implement chips and...**experience** **in the following areas:** - Physical Design - Place & Route tool experience on Cadence… more
- NVIDIA (Santa Clara, CA)
- …exposure to synthesis, clocks, DFT, power distribution, timing, and place & route . Previous experience as a physical design engineer would be ideal. + ... times per day. We are seeking a CAD R&D Engineer excited to innovate in algorithms related to ECO...thorough understanding of both VLSI hardware design and efficient software implementations is key. Experience with GUIs would also… more
- Cisco (San Jose, CA)
- Cisco Service Provider Solutions Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1444163) + Location:Offsite, San Jose, California, US + Alternate ... **Meet the Team** Cisco is seeking a highly motivated and experienced Solutions Engineer to join our team in a pre-sales technical and architectural role, partnering… more
- Qualcomm (Santa Clara, CA)
- …VHDL, etc.). * 6+ years of work experience with industry standard tools for synthesis place and/or route and design verification. * 6+ years of work experience ... to help create a smarter, connected future for all. As a Qualcomm CPU Engineer , you will lead innovative Central Processing Unit (CPU) design efforts that have a… more
- Amazon (Cupertino, CA)
- …design: full chip floorplanning, circuit analysis, power/clock distribution, timing optimization, place and route , power integrity analysis, and physical ... design and build every component of our hardware and software to come together into products that our customers...design, Clock/Power Distribution, Spice Circuit analysis - Experience with Place and Route , digital implementation - Experience… more
- Cisco (San Jose, CA)
- …+ Work closely with the physical design team to close design timing and place -and- route issues. + Triage, debug, and root cause simulation, software ... Senior ASIC Design Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1431806) + Location:San Jose, California, US...Cisco's flexible Vacation Time Off policy, which does not place a defined limit on how much vacation time… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …customers in the areas of Digital Design Implementation & Signoff including Synthesis, Place and Route , Design Closure, and timing/power signoff + Guide ... Understands ASIC Design implementation process and steps + Strong hands-on experience with Place & Route (Innovus, ICC2, Fusion Compiler) + Exposure and… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …designs. . Work on In-design timing ECO optimizations solutions with basic knowledge of Place and Route , Clock Tree, RC Extraction and UPF/CPF concepts. . ... tool bug fixes. Work on various aspects of physical design including timing analysis, place and route , extraction, spice etc. The annual salary range for… more
- NVIDIA (Santa Clara, CA)
- …tools + Good exposure to cross functional areas including RTL & clocks design, STA, place -n- route and power, to ensure we are making the right trade-offs + ... We are now looking for a Senior ASIC Design Engineer - DFX NVIDIA has continuously reinvented itself over...debugging tools + Work with other architects, platform and software teams to define feature set for future designs.… more
- Broadcom (San Jose, CA)
- …industry standards in Physical Design, Physical aware synthesis, Floorplanning, CTS and place and route .** + **Experience in developing and implementing ... is looking for a senior level ASIC physical design engineer . In this highly visible role, you will be...and supplies a broad range of semiconductor and infrastructure software solutions. For more information please visit our video… more