• Sr Principal ASIC

    Palo Alto Networks (Santa Clara, CA)
    …deliver the digital logic that powers our next-generation firewall platforms. As a Senior Principal Engineer, you will take end-to-end ownership of complex ... less experienced team members. This role requires a deep technical background in ASIC design for networking applications and the ability to independently drive… more
    Palo Alto Networks (07/11/25)
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  • Sr . Staff Design Engineer (Low…

    Qualcomm (Santa Clara, CA)
    …Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design , verification, validation, integration, or related work experience. OR ... Master's degree in Science, Engineering, or related field and 5+ years of ASIC design , verification, validation, integration, or related work experience. OR PhD… more
    Qualcomm (07/09/25)
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  • Rtl2gds IC Sr . Principal Solutions…

    Cadence Design Systems, Inc. (San Jose, CA)
    …related experience in design and EDA (Digital Implementation/Signoff) + Understands ASIC Design implementation process and steps + Strong hands-on experience ... + Provide technical support to Cadence customers in the areas of Digital Design Implementation & Signoff including Synthesis, Place and Route, Design Closure,… more
    Cadence Design Systems, Inc. (07/09/25)
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  • Principal Engineer - Silicon One Software

    Cisco (San Jose, CA)
    …are received. **Meet the Team** Cisco Silicon One is the center of Cisco's ASIC design and is driving the development of next-generation network devices for ... Principal Engineer - Silicon One Software Apply (https://jobs.cisco.com/jobs/Login?projectId=1443934)...design teams to define the next generation of ASIC products being developed. You will work multi-functionally with… more
    Cisco (07/05/25)
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  • RF/Analog IC Design Engineer

    Qualcomm (Santa Clara, CA)
    …RF/Analog circuits for wireless products (eg, LNA's, PLL's) and 4+ years of ASIC design , verification, or related work experience. OR Master's degree in ... Electrical Engineering or related field and 4+ years of ASIC design , verification, or related work experience....of work experience in a role requiring interaction with senior leadership (eg, Director and above). ** Principal more
    Qualcomm (05/29/25)
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