- Broadcom (San Jose, CA)
- …and develop scalable and reusable Testbench environment using the framework of Verification Methodologies. . Drive Test plans for all features for Block/Core/SOC and ... and get to full Functional coverage and bring the Verification to closure . Debug Regression failures, analyze Functional...in an efficient way. . Lead the documentation of verification strategy including Test plans, Verification Environment,… more
- Broadcom (San Jose, CA)
- …Architect and develop scalable and re-usable testbenches, using the framework of the verification methodology . Build pseudo-random tests to verify and get to full ... Coverage gaps and improve tests to cover the gaps . Document verification strategy including Test plans, Verification Environment, pseudo-random tests, etc.… more
- Power Integrations (San Jose, CA)
- …and power density. We are seeking a highly motivated Sr. Staff CAD Engineer to join our dynamic engineering team in capitalizing on this market transformation. ... Duties and Responsibilities + Develops and maintains PDKs. + Supports all IC design CAD tools such as Cadence schematic entry, mixed mode circuit simulation, layout… more
- Broadcom (San Jose, CA)
- …**Job Description:** Broadcom Inc. is looking for a creative and self motivated Digital IC Design Engineer to join the Data Center Solutions Group . This ... integrating third-party IP. * Working with cross functional teams such as Verification , Firmware and Systems Engineering to deliver detailed testing strategies and… more
- Broadcom (San Jose, CA)
- …Candidate Account, please Sign-In before you apply.** **Job Description:** **Job Description: IC Design Engineer ** + Participate in IP level architectural ... and Clock/Reset Domain crossing issues in the design + Collaborate with verification team on test plan development, debugging, and coverage closure + Collaborate… more
- Broadcom (San Jose, CA)
- …with custom routing for high speed interfaces, bump map design , routing and physical verification and tapeout to the foundries. As part of your job you will be ... (3DIC compiler), Mentor Graphics (Calibre) for layout generation, editing and verification + Strong understanding of TSV design, micro-bumps, solder bumps, and… more
- Broadcom (San Jose, CA)
- …have a Candidate Account, please Sign-In before you apply.** **Job Description:** Engineer will be responsible for verification of complex switch designs. ... Responsibilities will include creating SystemVerilog-based verification environments (testbenches, checkers, transactors) as well as creating...designs at both the block and chip level. The engineer will also be tasked with creating ATE testing… more
- Broadcom (San Jose, CA)
- …Candidate Account, please Sign-In before you apply.** **Job Description:** R&D Engineer position available in design and physical implementation of high performance ... Familiarity with VLSI design tools for Place&Route, Verilog simulation, DRC/LVS verification , Timing analysis (STA), Scripting languages - Tcl?Perl/ Python +… more
- Broadcom (San Jose, CA)
- …signal circuits subject to multiple constraints + Debug LVS/DRC/ERC errors with verification tool + Collaborate with design and layout engineers to optimize layout ... Work with CAD, packaging and foundry teams in resolving layout and / or verification issues + Experience required on technologies: 40nm, 16nm / 7nm FinFet -Knowledge… more
- Siemens (Fremont, CA)
- …This Applications Engineer (AE) position delivers technical expertise for Functional Verification of digital, mixed-signal, and analog IC chip designs based ... who like to interact with and influence others, possess strong design and/or verification background, requiring both in depth knowledge of HDL and HVL, as well… more
- Siemens (Fremont, CA)
- …This Applications Engineer (AE) position delivers technical expertise for Functional Verification of digital, mixed-signal, and analog IC chip designs based ... across a range of areas from application engineering support and management, verification and validation of complex semiconductor ICs, system testing, and beyond? If… more
- The Boeing Company (Mountain View, CA)
- …Systems has an exciting opportunity for multiple **ASIC and/or FPGA Design and Verification Engineers** (Experienced, Lead, or Senior) to join us as part of our ... high-integrity, low SWAP-C flight computers. And we're applying the latest digital IC design processes with industry-best tools to enable applications that cut… more
- Power Integrations (San Jose, CA)
- The role of the Principal Product Definition Engineer is to analyze customer requirements, create full application solutions and specify new integrated circuits ... In the process of specifying new integrated circuits, the Senior Systems Engineer will use advanced simulation techniques to develop algorithms and prototype… more
- Power Integrations (San Jose, CA)
- Job Description: The Senior Failure Analysis Engineer will perform power supply or system level failure analysis to support RMA and internal/external customer ... include, but are not limited to, the following. + Debugging and functionality verification of AC/DC switching power supply modules in various topologies using Power… more
- Siemens (Fremont, CA)
- …of 8 years of experience in IC design, either as a CAD or Design Engineer , or working with EDA tools. + Strong expertise in creating Place & Route test cases and ... enable companies around the world to develop new and highly innovative electronic IC products faster and more cost-effectively. Our customers are engineers who use… more
- Capgemini (San Francisco, CA)
- **Job description:** **Senior Analog Layout Engineer ** will be responsible for layout of high-performance analog cores such as analog-to-digital converters, ... digital-to-analog converters, PLL, transceivers, etc. Responsibilities include leading IC layout of cutting-edge high-performance, high-speed CMOS integrated circuits… more
- Renesas (San Jose, CA)
- Senior Staff Analog Engineer Job Description + Specify and design of CMOS circuits meeting performance, area, power, and timescale constraints + Run analog/mixed ... signal verification simulations at block and/or chip level. + Collaborate...have a consulting function in design reviews + Reviews IC design, evaluation, characterization and test results. + Schedule… more
- Cisco (San Jose, CA)
- …will also engage closely with engineering bring-up and diagnostics teams, test & verification teams, and Product Quality teams to identify and analyze key component ... Engineering, Physics, or related fields. * 12+ years of experience in IC Quality, Reliability, test, bring-up, validation, and characterization. * Experience in … more
- Cisco (San Jose, CA)
- …Leader, you will be responsible for overseeing the design and verification of application-specific integrated circuits (ASICs), ensuring they meet performance, ... PV issues and address to proper owners. * Deploy and improve physical verification flows and methodologies. Develop custom check as per need for verification… more
- Celestica (San Jose, CA)
- …an unrelenting drive to find the way for our customers. Let's engineer the future together. Responsible for architecting, implementing, and supporting power system ... create and maintain the preferred list + DC relevant IC selection, create and maintain the preferred list +...bring up, debug, and validation in the lab. + Verification Write and execute test and DVT plans. **Experience:**… more