- Siemens (Fremont, CA)
- Job Family: Software Req ID: 461784 Company: Siemens EDA Job Title: Product Engineer - RTL Synthesis Job Reference #: 461784 Job Location: Wilsonville, OR, ... is looking for a new team member to help define, promote and deploy our RTL FPGA Synthesis solutions of our Precision product line. You will join the… more
- Arrow Electronics (San Jose, CA)
- **Position:** Senior ASIC Design Engineer (eInfochips Inc) **Job Description:** **What candidate will Be Doing:** + Map multi-million gate SoC designs onto ... prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA ...our prototyping methodology. + **Option to engage in block-level RTL design or block or top-level IP integration.** +… more
- Siemens (Fremont, CA)
- …CE, CS or related areas Technical: * SystemVerilog, Verilog and VHDL RTL design experience * FPGA implementation experience(partitioning, synthesis, place&route) ... * Work closely with R&D to solve problems, review product specs, and find good general solutions that improve...SystemC and/or C/C++ is a plus * Debug of RTL designs and simulation * Proficient in scripting languages… more
- Siemens (Fremont, CA)
- …ASICs and SoCs, Failure analysis and resolution, Coverage analysis, RTL / Gate -simulations, Regression debug and other flow/infrastructure development and ... expect competent leadership from our managers and executives. This Applications Engineer (AE) position delivers technical expertise for Functional Verification of… more
- Siemens (Fremont, CA)
- …ASICs and SoCs, Failure analysis and resolution, Coverage analysis, RTL / Gate -simulations, Regression debug and other flow/infrastructure development and ... EDA could be the place for you! Job Description: This Applications Engineer (AE) position delivers technical expertise for Functional Verification of digital,… more
- quadric.io, Inc (Burlingame, CA)
- …processor architecture by understanding its applications + Own microarchitecture definition & RTL implementation of the processor in SystemC or SystemVerilog + Own ... Performance & Area (PPA) optimization + Contribute to timing closure through full product cycle (front end, back-end, tapeout) Requirements: + BS/MS or Ph.D. in… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …architecture coupled with hands-on Embedded Software (C/C++/Assembly) background is mandatory. RTL design and EDA/ FPGA implementation background is a plus. ... intelligent sensor computing SOCs. Join our winning team! As a Senior Field Applications Engineer in the San Jose Area, you will work closely with our sales,… more