- SanDisk (Milpitas, CA)
- …forward. **Job Description** We are looking for an experienced **Digital Physical Design Engineer ** to work whole digital SPR flow from RTL to GDS, include ... Synthesis, DFT scan insertion, PNR, STA timing analysis, IRdrop power analysis, DRC/LVS verification. Experienced...and analysis timing, routing issue in routeOpt stage, + ** STA timing analysis** + MMMC timing analysis using PT… more
- Broadcom (San Jose, CA)
- …Sign-In before you apply.** **Job Description:** Broadcom is looking for a senior level STA engineer . In this highly visible role, you will be contributing to ... timing constraints for intricate SoC designs. + Perform static timing analysis ( STA ) using industry-standard tools (eg, PrimeTime, Tempus). + Define and implement… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …on SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing, Distributed and Concurrent STA flows. . Work efficiently with R&D and customer to enable various ... timing analysis & ECO flows including newer advanced technologies. . Performing timing correlation, tool feature benchmarking, constraints validation, spice analysis on various tech nodes and customer designs. . Work on In-design timing ECO optimizations… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and ... and validate flows for Prime-Time , Prime-Shield and Tempus STA QoR metrics for sign-off flow, and tool for...std cells and custom IPs. + Develop flows/recommendations on STA sign-off to model deep submicron physical effects aging,… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are seeking an innovative Timing Methodology Engineer to help drive multi-physics sign-off strategies for the world's leading ... and validate flows for Prime-Time , Prime-Shield and Tempus STA QoR metrics for sign-off flow, and tool for...std cells and custom IPs. + Develop flows/recommendations on STA sign-off to model deep submicron physical effects aging,… more
- NVIDIA (Santa Clara, CA)
- …and intelligence. We are now looking for a motivated Senior ASIC Test Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... or MS (or equivalent experience) with 2+ years' experience in Timing and STA + Hands-on experience in full-chip/sub-chip Static Timing Analysis ( STA ) and… more
- MetaOption, LLC (Milpitas, CA)
- Physical Design Engineer - Milpitas, CA We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our client who designs and ... experience. Local candidates are preferred. Key Responsibilities: + Pre-layout STA for feasibility and timing constraint validation + Chip/block-level floorplanning… more
- Broadcom (San Jose, CA)
- …Account, please Sign-In before you apply.** **Job Description:** **Principal DFT Engineer ** Broadcom's ASIC Product Division is seeking candidates for a DFT ... metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role...and other I/P DFT integration + Working closely with STA and DI Engineers design closure for test +… more
- Meta (Sunnyvale, CA)
- **Summary:** We are looking for a Digital Design Engineer to support our Reality Labs Silicon AI Research team. We build research silicon to demonstrate and ... next generation AI and AR solutions.As a Digital Design Engineer (DDE), you will be a key contributor in...(DV) 3. Support back end physical design (PD) through STA and SDCs 4. Develop system tests in C… more
- Amazon (Cupertino, CA)
- …of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and architectures, while ensuring ... physical design, and methodologies including synthesis, place and route, STA , IR, formal and physical verification. - Demonstrated level...in PD tools such as Innovus, ICC2, Fusion Compiler, STA , and Sign-Off. - Proven track record of delivering… more
- Amazon (Cupertino, CA)
- …AI services for our customers' businesses. We are seeking experienced Physical Design Engineer to build the next generation of our cloud server platforms. Our ... design, physical design flows, and methodologies including synthesis, place and route, STA , formal verification. - Proven track record of delivering metric driven… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... and Timing + Hands-on experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints generation and management, and timing convergence. +… more
- NVIDIA (Santa Clara, CA)
- …a lasting impact on the world! We are currently looking for a Senior Methodology Engineer to develop and support our CAD tooling in our Circuit Solutions Group ! In ... VLSI CAD flows and methodology + Timing closure and STA tool experience required + Good programming skills in...+ Experience with .lib characterization flow or other related STA flows + Enjoy working with multiple levels and… more
- Broadcom (San Jose, CA)
- …desired PPA metrics. Candidate would also be required to do equivalence checks, STA , Timing closure and power optimization. Should be able to implement timing and ... **Requirements:** + Primary expertise in place and route and/ or timing (constraints, STA ) can be considered for this position. + Extremely proficient in design… more
- SpaceX (Sunnyvale, CA)
- Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars is ... with the ultimate goal of enabling human life on Mars. PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ASIC Physical Design Methodology/CAD Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is ... of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN METHODOLOGY/CAD ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building… more
- Broadcom (San Jose, CA)
- …Broadcom's ASIC Product Division is seeking candidates for HBM/DDR/SERDES Verification Lead Engineer position at our San Jose, California Development Center. We are ... seeking a highly skilled HBM and SerDes DFT Verification Engineer to join our dynamic team. In this role,...drive innovation within the team. + Working closely with STA and DI Engineers design closure for test +… more
- Texas Instruments (Santa Clara, CA)
- …chips both at the circuit level and behavioral level. As a design engineer , you will prepare test methods and specifications, assist in preparation of application ... participation in work groups, providing ideas and collaborative teamwork. **Why TI?** + Engineer your future. We empower our employees to truly own their career and… more
- NVIDIA (Santa Clara, CA)
- …closure across multi-billion transistor chips. We are seeking an Applied AI Engineer to lead end-to-end solution development - spanning data generation, model ... debugging. + Implement scalable orchestration across Flow-Server and Digital Engineer platforms, enabling AI-in-loop decision-making for sign-off readiness. +… more
- Google (Sunnyvale, CA)
- Physical Design Flow and Methodology Engineer _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving problems, and mentoring ... verification (Caliber/IC Validator), Formal Verification (LEC), Extraction, Low Power Verification, STA closure, and ECO flows. + Familiarity with 2.5D/3D IC… more
