- Amazon (Cupertino, CA)
- …massive scale and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and ... Amazon's Simple Storage Service (S3) and Amazon Elastic Compute Cloud (EC2), to consistently released new product innovations that...signal routing - As a key member of the ASIC design team, you will implement and… more
- Amazon (Cupertino, CA)
- … design quality and making the right trade-offs. Key job responsibilities As an ASIC Design Engineer , you will: * Develop and implement high-performance, ... a highly reliable, scalable, low-cost infrastructure platform in the cloud that powers hundreds of thousands of businesses in...rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze… more
- Google (Sunnyvale, CA)
- …of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Design Engineer , you will play an important role in designing ... a related field. + 5 years of experience in Application-specific integrated circuit ( ASIC ) design . + Experience working on interconnects and network subsystems.… more
- Arrow Electronics (San Jose, CA)
- **Position:** Senior ASIC Design Engineer (eInfochips Inc) **Job Description:** **What candidate will Be Doing:** + Map multi-million gate SoC designs onto ... prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA...by a minimum of 10 years of experience in ASIC or a related field, or a Master's Degree… more
- Google (Sunnyvale, CA)
- …and its integration within AI/ML-driven systems. As an Application-Specific Integrated Circuit ( ASIC ) Physical Design Engineer on the Chip Implementation ... practical experience. + 3 years of experience in physical design and methodologies. + Experience with place and route...ASICs in advanced technology nodes. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and… more
- Google (Sunnyvale, CA)
- …at RTL using SystemVerilog for ASICs. + Experience in memory subsystem design verification. + Experience in Power aware verification, Gate level simulations, and ... Post silicon bring-up. + Familiarity with ASIC standard interfaces and memory system architecture. In this...behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs,… more
- Google (Sunnyvale, CA)
- …a related field, or equivalent practical experience. + 3 years of experience in ASIC design or equivalent practical experience. + Experience in chip power ... efficiency, and integration. As part of the TPU Power Design team, you will play a pivotal part in...in pre and post silicon. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and… more
- Amazon (Cupertino, CA)
- …for in the United States. In Annapurna Labs we are at the forefront of hardware co- design not just in Amazon Web Services (AWS) but across the industry. The work we ... while also being deeply important to our customers. We design and build every component of our hardware and...is a fantastic choice. As a member of the Cloud -Scale Machine Learning Acceleration team you'll be responsible for… more
- Google (Sunnyvale, CA)
- …and networking equipment. + Experience in hyperscale data center networking, and ASIC design and implementation. Preferred qualifications: + PhD in Electrical ... to networking, complex ASICs, ML, GPU systems, and infrastructure design and implementation. As the Principal Engineer ...commodity management. + Work closely with the Data Center, ASIC , Platforms, and Google Cloud teams to… more
- Amazon (Cupertino, CA)
- …today's AI workloads in datacenters all around the world. As a Circuit & Design Analysis engineer , you'll collaborate with multiple teams to drive improvements ... here at Amazon! We're searching for an experienced Circuit Design & Analysis engineer with a background...transistor fundamentals in deep sub-micron processes - Understanding of ASIC Physical Design from RTL-to-GDSII - Understanding… more
- Google (Sunnyvale, CA)
- …Computer Science, with an emphasis on computer architecture. + 10 years of experience in ASIC design with 3 years of experience working on security design . ... delivering unparalleled performance, efficiency, and integration. As a SoC Design Engineer , you will join a team...software and system hardware counterparts. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and… more
- Amazon (Cupertino, CA)
- …handling massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze new ... a highly reliable, scalable, low-cost infrastructure platform in the cloud that powers hundreds of thousands of businesses in...MS + 6yrs in EE/CS - 6+ years in ASIC Physical Design from - RTL-to-GDSII in… more
- Google (Sunnyvale, CA)
- …TPU architecture and its integration within AI/ML-driven systems. As a Custom Datapath Physical Design Engineer on the Chip Implementation team, you will work on ... equivalent practical experience. + 10 years of experience in ASIC physical design and methodologies in advanced...ideas into our flows and designs.The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and… more
- Amazon (Cupertino, CA)
- …machine learning and AI services for our customers' businesses. We are seeking experienced Physical Design Engineer to build the next generation of our cloud ... responsibilities - You will create and support innovative physical design methodology and CAD flows. - Develop cloud...in TCL, Perl, and/or Python - Solid understanding of ASIC physical design , physical design … more
- Google (Sunnyvale, CA)
- …or equivalent practical experience. + 6 years of experience working in a hardware systems design , or 5 years of experience with an advanced degree. + 3 years of ... experience in technical leadership. + Experience with power circuit design and signal integrity. Preferred qualifications: + PhD in...DDR, Ethernet, USB, SPI, etc. As a Staff Hardware Engineer , you will work on Machine Learning/AI hardware systems… more
- Google (Sunnyvale, CA)
- …analysis and timing ECO creation, timing margins). + Experience with Electronic Design Automation (EDA) tools (ie, Primetime, Tempus, Timevision, STAR-RC) and EDA ... static timing analysis. + Experience leading one or more aspects of physical design or physical design flow/methodology, to successful tape-outs and shipping… more
- Capgemini (San Jose, CA)
- …data structures, and algorithms. The ideal candidate will have experience in ASIC design and development within Linux-based environments. Proficiency in version ... and optimize data structures and algorithms to solve complex problems. + Support ASIC design and verification processes. + Develop and manage projects in… more
- Microsoft Corporation (Santa Clara, CA)
- As a Silicon Engineer - ASIC verification in the Data Processing Unit team you will be validating silicon to solve complex problems in a datacenter. You will ... to the next stage in your career Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team...achieve that mission. We are looking for a **Silicon Engineer ** to join our team! **Responsibilities** + Perform functional… more
- Capgemini (San Jose, CA)
- …system. + Experience building or working with real-time embedded systems. + Knowledge of ASIC design flow and ASIC prototyping flow. + Experience with ... **About the job you're considering** As a Software Infrastructure Engineer , you will be part of the End-to-End (E2E)...FPGA and hardware evaluation boards, EDA design tools, and/or ISA simulators. **Basic qualifications:** + BS… more
- Microsoft Corporation (Santa Clara, CA)
- …for passionate, high-energy engineers to help achieve that mission. As a Senior Silicon Engineer - ASIC verification in the Data Processing Unit team you will ... Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...+ Lead key components of functional validation of complex ASIC SOC using UVM/C test bench + Perform pre-silicon… more